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publications
A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique
Published in IEEE ISSCC2017., 2017
We propose a power efficient amplifier for switched capacitor circuits.
Recommended citation: Yoshioka, Kentaro. (2018). "A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique." IEEE ISSCC.
A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique
Published in ISSCC 2018, 2018
200m automobile LiDAR SoC for self-driving.
Recommended citation: Yoshioka, Kentaro. (2018). "A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique." ISSCC. https://ieeexplore.ieee.org/abstract/document/8310199
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators
Published in IEEE VLSI 2018, ASSCC 2018, JSSC 2019., 2018
A power efficient MAC circuit for DNN computation is proposed.
Recommended citation: Yoshioka, Kentaro. (2018). "PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators." IEEE ICIP.
Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models
Published in IEEE ICIP 2019, 2019
We propose Dataset Culling: a pipeline to reduce the size of the dataset for training.
Recommended citation: Yoshioka, Kentaro. (2019). "Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models." IEEE ICIP.
Successive-Approximation Based CMOS Process-Scalable Hybrid ADCs
Published in Ph.D thesis., 2019