A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique
Yoshioka, Kentaro. (2018). "A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique." IEEE ISSCC.
CV
Education
- B.S. in Electronical Engineering, Keio University, Japan (2012)
- M.S. in Electronical Engineering,, Keio University, Japan (2014)
- Ph.D in Electronical Engineering, Keio University, Japan (2019)
Work experience
- 2014-2016: ADC Circuit Designs
- Toshiba Research Scientist
- Lead ADC designs for wireless products (WiFi chips)
- 2016-2018: LiDAR System Designs
- Toshiba Research Scientist
- Lead analog designs for LiDAR SoCs
- 2017-2019: Machine Learning System Designs
- Stanford Visiting Scholar
- Systems for efficient machine learning systems.
Skills
Competitive research skills (400 citations) https://scholar.google.co.jp/citations?user=jSxIrBEAAAAJ&hl=en&authuser=1
Distinguished hardware design skills
Experience in 3 products (LiDARx2, WiFi)
Publications in top-tier conferences (ISSCC,VLSI,ICIP)
- Competitive data science skills (Kaggle Expert) https://www.kaggle.com/kyoshioka47
Publications
A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique
Yoshioka, Kentaro. (2018). "A 20ch TDC/ADC hybrid SoC for 240× 96-pixel 10%-reflection< 0.125%-precision 200m-range imaging LiDAR with smart accumulation technique." ISSCC.
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators
Yoshioka, Kentaro. (2018). "PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators." IEEE ICIP.
Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models
Yoshioka, Kentaro. (2019). "Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models." IEEE ICIP.