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ISSCC · 2022–2026 LIVE

Beijing Institute of Technology

対象論文Papers 4 · 筆頭著者first author 1 · 著者按分fractional 1.40 · 中国China #16 · 世界World #69

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Qirui Chen ORCID2
1Xiaoran Li ORCID2
1Xinghua Wang ORCID2
1Yiming Yang ORCID2
5Guangzhong Zhang1
5Houjun Sun1
5Jiazhi Ying1
5Meini Tang1
5Naike Du1
5Shidong Lv1
5Wei Zhu ORCID1
5Xi Wei1
5Xiuzhu Ye1
5Zhiqiang Zhao1
5Zhixian Hou1
5Zunxiang Wang1

対象論文Papers

  1. ISSCC
    2026
    A 1.6-to-3.8GHz Reconfigurable FMCW Radar SoC with 81.5% Relative-Bandwidth PLL for Real-Time Life Detection in Disaster Response
    DOI
    Renjie Fu, Linxu Shi, Fanxun Cai, Yunqi Yang, Hao Lei, Zhigang Fu, Yilin Xu, Pengcheng Wang, Ziyang Li, Shixuan Wang, Junkai Jiao, Dingqi Liang, Lianbo Wu, Guangzhong Zhang, Naike Du, Zijie Wang, Yucong Gu, Xiuzhu Ye, Xiao Fang, Weisheng Zhao, Hui Zhang
    Beihang University · Beijing Institute of Technology
  2. ISSCC
    2025
    14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference
    DOI
    Yiyang Yuan, Bingxin Zhang, Yiming Yang, Yishan Luo, Qirui Chen, Shidong Lv, Hao Wu, Cailian Ma, Ming Li, Jinshan Yue, Xinghua Wang, Guozhong Xing, Pui-In Mak, Xiaoran Li, Feng Zhang
    Chinese Academy of Sciences · Beijing Institute of Technology · University of Macau
  3. ISSCC
    2024
    32.8 A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving 27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB Back-Off Efficiency
    DOI
    Wei Zhu, Jiazhi Ying, Long Chen, Jian Zhang, Guanshen Lv, Xiangjie Yi, Zhiqiang Zhao, Zunxiang Wang, Yan Wang, Wenhua Chen, Houjun Sun
    Beijing Institute of Technology · Tsinghua University
  4. ISSCC
    2024
    34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC
    DOI
    Yiyang Yuan, Yiming Yang, Xinghua Wang, Xiaoran Li, Cailian Ma, Qirui Chen, Meini Tang, Xi Wei, Zhixian Hou, Jialiang Zhu, Hao Wu, Qirui Ren, Guozhong Xing, Pui-In Mak, Feng Zhang
    Chinese Academy of Sciences · University of Chinese Academy of Sciences · Beijing Institute of Technology · University of Macau