VLSI · 2022–2026 LIVE

Chinese Academy of Sciences

対象論文Papers 11 · 筆頭著者first author 8 · 著者按分fractional 5.47 · 中国China #1 · 世界World #7

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Ming Liu ORCID	4
2	Chunmeng Dou ORCID	3
3	Bo Li	2
3	Feng Zhang ORCID	2
3	Hongyu Ren ORCID	2
3	Jinshan Yue ORCID	2
3	Liyuan Liu ORCID	2
3	Nan Qi ORCID	2
3	Xiaoxin Xu ORCID	2
3	Zeyu Guo	2
3	Zunsong Yang ORCID	2
12	Ang Li	1
12	Cailian Ma	1
12	Chenyang Zhong	1
12	Danian Dong	1
12	Dashan Shang ORCID	1
12	Fei Wang ORCID	1
12	Guike Li ORCID	1
12	Han Liu ORCID	1
12	Jian Liu ORCID	1
12	Kai Cheng	1
12	Kaiping Zhang	1
12	Li Wang ORCID	1
12	Liangjiang Zhou	1
12	Long Nie	1
12	Ming Li ORCID	1
12	Minye Zhu	1
12	Nanjia Jiang	1
12	Nanjian Wu ORCID	1
12	Peiwen Zhang	1
12	Renrui Fang	1
12	Rui Wu ORCID	1
12	Ruoyu Wu	1
12	Shengjie Zhao	1
12	Shengzhe Yan ORCID	1
12	Shuaidi Zhang	1
12	Tianle Chen	1
12	W. Rui	1
12	Weidong Zhang	1
12	Weiwei Yan	1
12	Weiye Tang ORCID	1
12	Wenxuan Sun	1
12	Woyu Zhang	1
12	Xianghe Meng	1
12	Xiaoyu Shan ORCID	1
12	Xiping Jiang ORCID	1
12	Xuan Guo ORCID	1
12	Xuqiang Zheng ORCID	1
12	Yang Qu	1
12	Yao Li	1
12	Yi Li ORCID	1
12	Yongliang Xiong	1
12	Yu Liu ORCID	1
12	Yujun Xie	1
12	Yunbo Huang ORCID	1
12	Zhao Zhang ORCID	1
12	Zhaori Cong ORCID	1
12	Zhaoyu Zhang	1
12	Zhuoyu Dai	1
12	Zi Wang	1

対象論文Papers

VLSI
2026

A 1.5-to-20.5 GHz Intrinsic-Spurious-Rejection Real-If Dual-Translation Transceiver Chipset Achieving 10-Gb/s 1024-QAM and 5-μs Hopping
DOI
Dongze Li, Yichi Sun, Wei Deng, Xiangyu Nie, Fuzhi Xue, Haikun Jia, Liangjiang Zhou, Rui Wu, Baoyong Chi

Tsinghua University · Chinese Academy of Sciences · Aerospace Information Research Institute
VLSI
2026

A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase Detector Achieving 53.8fs rms Jitter and −281.1dB FoM N
DOI
Yunbo Huang, Zunsong Yang, Li Wang, Kai Cheng, Hongyu Ren, Xiaoyu Shan, Pui-In Mak, Yong Chen, Bo Li

Chinese Academy of Sciences · University of Macau · Tsinghua University
VLSI
2025

A ${4} \times \text{112-Gb}/\mathrm{s}$, 3.51-pJ/Bit Monolithically Integrated Silicon-Photonic Transceiver for High-Density Co-Packaged Optics
DOI
Han Liu, Nan Qi, Ang Li, Minye Zhu, Yongliang Xiong, Ruoyu Wu, Yujun Xie, Yang Qu, Chenyang Zhong, Guike Li, Ming Li, Liyuan Liu

Chinese Academy of Sciences
VLSI
2025

First Implementation of Monolithic Integrated Cim with 1Mb Ultra-High-Density 8-Layer 3D VRRAM, Achieving High Computing Density ($204.8 \text{GOPs} / \text{mm}^{2}$) and FoM ($\mathbf{2. 1 3} \times \mathbf{1 0}^{\mathbf{6}} \text{GOPS}^{\mathbf{2}} / \mathbf{W} / \text{mm}^{\mathbf{2}}$) for Efficient Scientific Computing
DOI
Cailian Ma, Wenxuan Sun, Long Nie, Yao Li, Yue Wu, Zichen Fan, Weiye Tang, Kaiping Zhang, Yu Liu, Shengjie Zhao, Peiwen Zhang, Shuaidi Zhang, Xiaoxin Xu, Feng Zhang, Ming Liu

Chinese Academy of Sciences · Beijing Institute of Technology
VLSI
2024

A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System
DOI
Ruichen Wan, Wei Deng, W. Qixiu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, H. Sanming, Zhihua Wang, Baoyong Chi

Tsinghua University · Chinese Academy of Sciences · Aerospace Information Research Institute · Southeast University
VLSI
2024

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications
DOI
Zhuoyu Dai, Shengzhe Yan, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu

Chinese Academy of Sciences · Tsinghua University
VLSI
2024

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur
DOI
Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li

Chinese Academy of Sciences · University of Macau · 東京大学The University of Tokyo
VLSI
2023

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV
DOI
Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang

University of Science and Technology of China · Xi'an UniIC Semiconductors (China) · Chinese Academy of Sciences
VLSI
2023

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro
DOI
Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu

Chinese Academy of Sciences · Tsinghua University
VLSI
2023

A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS
DOI
Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu

Chinese Academy of Sciences · University of Chinese Academy of Sciences · University of Macau
VLSI
2022

Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory
DOI
Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, Chunmeng Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Ming Liu

Chinese Academy of Sciences · University of Chinese Academy of Sciences · University of Hong Kong · Rochester Institute of Technology