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VLSI · 2022–2026 LIVE

Hong Kong University of Science and Technology

対象論文Papers 12 · 筆頭著者first author 6 · 著者按分fractional 5.26 · 世界World #14

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Fengbin Tu ORCID5
2C. Patrick Yue3
3Li Wang ORCID2
3Zilu Liu ORCID2
5Bohan Yang ORCID1
5Chi-Ying Tsui ORCID1
5Chongyun Zhang ORCID1
5Fengshi Tian ORCID1
5Fuzhan Chen ORCID1
5H. Bruce Bao1
5Hao Yu1
5Haochen Yu1
5Hongwu Jiang ORCID1
5Jiancong Li1
5Jingyu He ORCID1
5Kwang-Ting Cheng ORCID1
5Longke Yan ORCID1
5Man Hoi Wong1
5Qiming Shao1
5R. Matthew Ma1
5Ruihao He1
5S. Sarah Feng1
5Shanshi Huang ORCID1
5Wing-Hung Ki ORCID1
5Xuezhao Wu1
5Yaoru Hou1
5Yixuan Jiang1
5Yuan Yao ORCID1
5Zefeng Xu1
5Zhihua Xiao1
5Zhiyu Liu ORCID1
5Zihao Deng1

対象論文Papers

  1. VLSI
    2026
    A 1.58-W/mm 2 Extreme-Power-Density Ka-Band GaN PA with Electro-Thermal-Mechanical Co-Design in CMOS+GaN Heterogeneous Integration
    DOI
    R. Matthew Ma, H. Bruce Bao, S. Sarah Feng, Zhiyu Liu, Yi Pei, Man Hoi Wong, C. Patrick Yue
    Hong Kong University of Science and Technology
  2. VLSI
    2026
    A 28nm 44.15TFLOPS/W and 1.57TFLOPS/mm 2 Joint-Alignment Floating-Point CIM Macro with ISO26262 ASIL-D Safety Level for Autonomous Driving
    DOI
    Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Yang Hu, Fengbin Tu, Shouyi Yin
    Tsinghua University · Hong Kong University of Science and Technology
  3. VLSI
    2026
    A 28nm CMOS-Integrated VCMA-MTJ Dual-Function Macro for Deterministic In-Memory Computing Synapses and Stochastic Poisson Neurons in Hybrid Vision
    DOI
    Yaoru Hou, Zhihua Xiao, Xuezhao Wu, Shuyu Wang, Zheng Zhu, Di Wu, Jiayong Wang, Yuesheng Li, Hao Cai, Qiming Shao
    Hong Kong University of Science and Technology · Southeast University · Shanghai University
  4. VLSI
    2026
    A 40nm 24.85-to-80.59 TFLOPS/W FP8 Computing-in-Memory Macro with Outlier-Aware Hierarchical-Alignment for Edge Transformers
    DOI
    Zhiwei Zhou, Tong Hu, Jia Chen, Jiancong Li, Yuyang Fu, Yi Li, Xiangshui Miao
    Huazhong University of Science and Technology · Hong Kong University of Science and Technology
  5. VLSI
    2026
    First Demonstration of High-Precision (15 Bits) Photonic-Electronic Hybrid Compute-in-Memory System Based on FeFET Pockels Photonic Memory
    DOI
    Haochen Yu, Yixuan Jiang, Ruihao He, Hao Yu, Zihao Deng, Hongwu Jiang, Shanshi Huang, Zefeng Xu
    Hong Kong University of Science and Technology · The Hong Kong University of Science and Technology (Guangzhou)
  6. VLSI
    2025
    A 6.78 MHz Multiple-Transmitter Wireless Power Transfer System with Integrated Coupling Coefficient Sensor
    DOI
    Yuan Yao, Fengshi Tian, Jingyu He, Wing-Hung Ki, Chi-Ying Tsui, Kwang-Ting Cheng, Yang Liu
    Hong Kong University of Science and Technology · Xidian University
  7. VLSI
    2025
    CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-Based Edge LLM Accelerator with 1.78ms-Response in Prefill and 31.32 Token/s in Decoding
    DOI
    Zihan Wu, Yiqi Wang, Zhen He, Bohan Yang, Yang Wang, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
    Tsinghua University · Hong Kong University of Science and Technology
  8. VLSI
    2025
    LLM-CIM: A 28nm 126.7TOPS/W Input-LUT-Based Digital CIM Macro with Reconfigurable Matrix Multiplication and Nonlinear Operation Modes for LLMs
    DOI
    Yiqi Wang, Zhen He, Zihan Wu, Ruiqi Guo, Longke Yan, Huiming Han, Yang Wang, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
    Tsinghua University · Hong Kong University of Science and Technology
  9. VLSI
    2024
    A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation
    DOI
    Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
    Tsinghua University · Hong Kong University of Science and Technology
  10. VLSI
    2024
    A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS
    DOI
    Chongyun Zhang, Li Wang, Zilu Liu, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue
    Hong Kong University of Science and Technology · Southern University of Science and Technology · Sun Yat-sen University
  11. VLSI
    2024
    ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction
    DOI
    Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
    Tsinghua University · Hong Kong University of Science and Technology
  12. VLSI
    2023
    A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and −248.6-dB FoMjitter
    DOI
    Li Wang, Zilu Liu, C. Patrick Yue
    Hong Kong University of Science and Technology