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企業・研究機関Company / Institute · 台湾Taiwan · 2022–2026 LIVE

Industrial Technology Research Institute

台湾Taiwan 4位 (48 pt) · 世界World 28位 (0 pt) · 対象論文Papers 17

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0123452022 ISSCC: 12022 VLSI: 12022 JSSC: 1320222023 ISSCC: 12023 VLSI: 12023 JSSC: 1320232024 ISSCC: 12024 VLSI: 22024 JSSC: 2520242025 VLSI: 12025 JSSC: 12025 CICC: 1320252026 ISSCC: 12026 JSSC: 232026
ISSCCVLSIJSSCCICC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC111–1
VLSI1121–
JSSC11212
CICC–––1–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1400.83台湾Taiwan #4 · 世界World #30
VLSI Tier 1533.50台湾Taiwan #3 · 世界World #14
JSSC Tier 1711.63台湾Taiwan #4 · 世界World #25
CICC Tier 2100.43台湾Taiwan #2 · 世界World #22
A-SSCC Tier 2000.00–
ESSERC Tier 2000.00–

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. ISSCC
    2026
    A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing
    DOI
    Yao-Kai Yeh, Jian-Wei Su, Ting-Hao Hsu, Mai Tseng, Jen-Chun Tien, Ko-Chi Chen, Chih-Yen Yue, Yu-En Lin, Yu-Jia Hu, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Hung-Hsi Hsu, De-Qi You, Sheu Shyh-Shyuan, Wei-Chung Lo, Shih-Chieh Chang, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · Industrial Technology Research Institute
  2. JSSC
    2026
    A 40-nm 209-TOPS/W Reinforcement Learning Processor With Full Speculation Exploitation and Inference-Training Parallel Processing
    DOI
    Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chih-Wei Liu, Chun-Lung Hsu, Chia-Hsiang Yang
    National Taiwan University · Industrial Technology Research Institute
  3. JSSC
    2026
    A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device
    DOI
    Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Industrial Technology Research Institute
  4. CICC
    2025
    A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing
    DOI
    Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chun-Lung Hsu, Chih-Wei Liu, Chia-Hsiang Yang
    National Taiwan University · Industrial Technology Research Institute
  5. JSSC
    2025
    An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips
    DOI
    Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Industrial Technology Research Institute
  6. VLSI
    2025
    Enabling Privacy-Preserving Collective Intelligence: A Twin In-Memory Encryption/Processing Macro Featuring Group Differential Privacy and Spatial-Temporal Ensemble
    DOI
    Bo-Cheng Chiou, Chih-Sheng Lin, Yun-Ting Ho, Yu-Hui Lin, I-Ta Wu, Kuo-Hua Tseng, Chih-Ming Lai, Peng-I Mei, Sih-Han Li, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
    Industrial Technology Research Institute · National Yang Ming Chiao Tung University
  7. ISSCC
    2024
    34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices
    DOI
    Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    TSMC · National Tsing Hua University · Industrial Technology Research Institute
  8. JSSC
    2024
    A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips
    DOI
    Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · Industrial Technology Research Institute
  9. JSSC
    2024
    An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips
    DOI
    Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · Industrial Technology Research Institute
  10. VLSI
    2024
    Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security
    DOI
    Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
    Industrial Technology Research Institute · National Yang Ming Chiao Tung University
  11. VLSI
    2024
    Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology
    DOI
    Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
    National Yang Ming Chiao Tung University · Industrial Technology Research Institute
  12. ISSCC
    2023
    A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices
    DOI
    Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · Industrial Technology Research Institute
  13. JSSC
    2023
    A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips
    DOI
    Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · Industrial Technology Research Institute
  14. VLSI
    2023
    A CMOS/Microfluidics Point-of-Care SoC employing Square-Wave Voltcoulometry for Biosensing with Aptamers and CRISPR-Cas12a Enzymes
    DOI
    Yan-Ting Hsiao, Shu-Yan Chuang, Hung-Yu Hou, Yun-Chun Su, Hsiu-Cheng Yeh, Hsin-Tzu Song, Yun-Jui Chang, Wei-Yang Weng, Ya-Chen Tsai, Pin-Yu Lin, Sih-Ying Chen, Yen-Ju Lin, Mei-Wei Lin, Jun-Chau Chien
    National Taiwan University · Industrial Technology Research Institute · University of California, Berkeley
  15. ISSCC
    2022
    A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices
    DOI
    Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho- Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang
    National Tsing Hua University · Industrial Technology Research Institute
  16. JSSC
    2022
    Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips
    DOI
    Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang
    National Tsing Hua University · Southeast University · Georgia Institute of Technology · Industrial Technology Research Institute
  17. VLSI
    2022
    An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology
    DOI
    Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu
    Industrial Technology Research Institute · National Yang Ming Chiao Tung University