JSSC · 2022–2026 LIVE

Kwangwoon University

対象論文Papers 6 · 筆頭著者first author 2 · 著者按分fractional 2.74 · 韓国Korea #11 · 世界World #76

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Joo-Hyung Chae ORCID	6
2	Chanheum Han ORCID	2
2	Ki-Soo Lee ORCID	2
4	Jongchan Lee ORCID	1
4	Jun-Cheol Lee ORCID	1
4	Kyuho Jason Lee ORCID	1

対象論文Papers

JSSC
2026

A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces
DOI
Jun-Cheol Lee, Joo-Hyung Chae

Kwangwoon University
JSSC
2026

DPIM: A 2T1C eDRAM Transformer-in-Memory Chip With Sparsity-Aware Quantization and Heterogeneous Dense–Sparse Core
DOI
Donghyuk Kim, Jae-Young Kim, Hyunjun Cho, Seungjae Yoo, Sukjin Lee, Sungwoong Yune, Sejeong Yang, Hoichang Jeong, Keonhee Park, Ki-Soo Lee, Jongchan Lee, Chanheum Han, Gunmo Koo, Yuli Han, Jaejin Kim, Jaemin Kim, Kyuho Jason Lee, Joo-Hyung Chae, Kunhee Cho, Joo-Young Kim

Korea Advanced Institute of Science and Technology · Kyungpook National University · Ulsan National Institute of Science and Technology · Kwangwoon University · Yonsei University · Sungkyunkwan University
JSSC
2025

25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies
DOI
Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae

Kwangwoon University
JSSC
2024

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces
DOI
Jaekwang Yun, Sangyoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong

Seoul National University · Samsung · Kwangwoon University · Sejong University
JSSC
2023

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces
DOI
Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim

Sejong University · Kwangwoon University · Seoul National University
JSSC
2022

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
DOI
Ji-Hyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gangsik Lee, Sangyeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seonyong Cha

SK hynix · Kwangwoon University