VLSI · 2022–2026 LIVE

Massachusetts Institute of Technology

対象論文Papers 6 · 筆頭著者first author 5 · 著者按分fractional 4.42 · アメリカUSA #8 · 世界World #35

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Anantha P. Chandrakasan ORCID	3
2	Hae-Seung Lee ORCID	2
3	Adam Gierlach	1
3	Anantha Chandrakasan	1
3	Deniz Umut Yildirim ORCID	1
3	Donghyeon Han ORCID	1
3	Eunseok Lee ORCID	1
3	Giovanni Traverso ORCID	1
3	Hanrui Wang	1
3	Hyemin S. Lee	1
3	Jaehong Jung ORCID	1
3	Jinchen Wang ORCID	1
3	Joel Emer	1
3	Peter Zhi Xuan Li	1
3	Rishabh Mittal ORCID	1
3	Ruicong Chen	1
3	Ruonan Han ORCID	1
3	Sertac Karaman	1
3	Vivienne Sze	1
3	Zih-Sing Fu	1

対象論文Papers

VLSI
2026

GMINI: Gut Modulating Neural Interface Chip for Closed-Loop Non-Invasive Therapies
DOI
Adam Gierlach, Hyemin S. Lee, Deniz Umut Yildirim, Giovanni Traverso, Anantha P. Chandrakasan

Massachusetts Institute of Technology
VLSI
2026

Gleanmer: A 6 mW SoC for Real-Time 3D Gaussian Occupancy Mapping
DOI
Zih-Sing Fu, Peter Zhi Xuan Li, Sertac Karaman, Vivienne Sze

Massachusetts Institute of Technology
VLSI
2025

A 55.8-to-64.2GHz, $58.3\text{fs}_{\text{rms}}$ -Jitter, $-250.2\text{dB-FoM}_{\mathrm{J}}$ Fractional-N Cascaded PLL in 28nm CMOS
DOI
Jaehong Jung, Eunseok Lee, Donghyeon Han, Jinchen Wang, Anantha P. Chandrakasan, Ruonan Han

Massachusetts Institute of Technology
VLSI
2024

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications
DOI
Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina

Stanford University · University of Southern California · Massachusetts Institute of Technology
VLSI
2023

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET
DOI
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee

Massachusetts Institute of Technology · Analog Devices
VLSI
2022

RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience
DOI
Ruicong Chen, Hanrui Wang, Anantha Chandrakasan, Hae-Seung Lee

Massachusetts Institute of Technology