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VLSI · 2022–2026 LIVE

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対象論文Papers 9 · 筆頭著者first author 5 · 著者按分fractional 5.26 · 台湾Taiwan #2 · 世界World #10

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Chih-Chen Li4
2Chien-Hung Lin3
2Tsung-Yao Lin3
4Cheng-Xin Xue2
4En-Jui Chang2
4Hung-Wei Lin2
4Jenwei Liang2
4Meng-Han Hsieh2
9Allen-CL Lu1
9Cheng-Ying Yu1
9Chetan Deshpande1
9Chia-Da Lee1
9Chia-Hsien Chou1
9Chia-Wei Hsu1
9Chiao-Chun Huang1
9Chieh-Fang Teng1
9Chien-Sheng Chao1
9Chih-Cheng Chen ORCID1
9Chih-Chung Cheng1
9Chung-Lun Huang1
9Fan-Wei Liao1
9Gajanan Jedhe1
9Hsien-Kai Kuo1
9Hsing-Chang Chou1
9Jeng-Yun Hsu1
9Kai-Siang Yang1
9Kou-Hung Lawrence Loh1
9Kun-Geng Lee1
9Kuo-Sheng Wu1
9Perry H. Wang1
9Po-Hua Huang1
9Shan-Chih Tsou1
9Shiyi Ou1
9Tun-Yi Chang1
9Wei-Ting Hung1
9Yi-Chen Chu1
9Yi-Min Tsai1
9Yi-Yen Hsieh ORCID1
9Yucheun Kevin Jou1
9Zhe Wan1

対象論文Papers

  1. VLSI
    2026
    TinyNPU: A3nm 0.06-134.36 μJ/Token DCIM-Based Ultra Low Power NPU for Always-On Reasoning on Wearables
    DOI
    Yi-Yen Hsieh, En-Jui Chang, Chieh-Fang Teng, Po-Hua Huang, Hsien-Kai Kuo, Hsing-Chang Chou, Kai-Siang Yang, Shiyi Ou, Chiao-Chun Huang, Cheng-Xin Xue, Wei-Ting Hung, Zhe Wan, Hung-Wei Lin, Gajanan Jedhe, Yi-Chen Chu, Tun-Yi Chang, Chia-Hsien Chou, Kun-Geng Lee, Perry H. Wang, Chetan Deshpande, Jenwei Liang, Chien-Hung Lin, Tsung-Yao Lin, Yucheun Kevin Jou
    MediaTek
  2. VLSI
    2025
    Enabling Generative AI: Innovations and Challenges in Semiconductor Design Technologies
    DOI
    Kou-Hung Lawrence Loh
    MediaTek
  3. VLSI
    2024
    A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6% High Efficiency and Fast Transient Response
    DOI
    Yu-Chen Kuo, Hong-Teng Wu, Guan-Ye Chen, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li
    National Yang Ming Chiao Tung University · MediaTek
  4. VLSI
    2024
    A 15.4ppm/○C GaN-based Voltage Reference with Process-Variation-Immunity and High PSR for EV Power Systems
    DOI
    Po-Jui Chiu, Tz-Wun Wang, Chi-Yu Chen, Sheng-Hsi Hung, Yu-Ting Huang, Xiao-Quan Wu, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li
    National Yang Ming Chiao Tung University · MediaTek
  5. VLSI
    2024
    A Monolithic Low-ILEAK Cross-Coupled GaN Driver with ΔΦ-Reduced EMI-Rejecter for 21.51dBµV-EMI-Reduction and 1/10x filter-capacitor
    DOI
    Hsing-Yen Tsai, Shi-Jun Zeng, Yu-Teng Liang, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li
    National Yang Ming Chiao Tung University · MediaTek
  6. VLSI
    2024
    A Quad-Core AI Processing Unit for Generative AI in 4nm 5G Smartphone SoC
    DOI
    Chien-Hung Lin, Jeng-Yun Hsu, Cheng-Ying Yu, Chia-Wei Hsu, Yi-Min Tsai, Kuo-Sheng Wu, Chung-Lun Huang, Meng-Han Hsieh, Tsung-Yao Lin
    MediaTek
  7. VLSI
    2024
    A ±100A Auto-Calibration Current Sensor with 80V Pulse-Width Modulation Attenuation and 0.15% Gain Error
    DOI
    Yu-Teng Liang, Shi-Jun Zeng, Yu-Tse Shih, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li
    National Yang Ming Chiao Tung University · MediaTek
  8. VLSI
    2023
    A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision
    DOI
    En-Jui Chang, Cheng-Xin Xue, Chetan Deshpande, Gajanan Jedhe, Jenwei Liang, Chih-Chung Cheng, Hung-Wei Lin, Chia-Da Lee, Sushil Kumar, Kim Soon Jway, Zijie Guo, Ritesh Garg, Allen-Cl Lu, Chien-Hung Lin, Meng-Han Hsieh, Tsung-Yao Lin, Chih-Cheng Chen
    MediaTek · MediaTek
  9. VLSI
    2023
    A 6nW 30.8kHz Relaxation Oscillator with Sampling Bias-Free RC Circuit and Dynamic Power Scaling in a 12nm FinFET
    DOI
    Fan-Wei Liao, Shan-Chih Tsou, Chien-Sheng Chao
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