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企業・研究機関Company / Institute · 韓国Korea · 2022–2026 LIVE

SK hynix

韓国Korea 2位 (72 pt) · 世界World 8位 (14 pt) · 対象論文Papers 47

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0246810122022 ISSCC: 42022 VLSI: 12022 JSSC: 62022 A-SSCC: 11220222023 ISSCC: 22023 VLSI: 12023 JSSC: 72023 A-SSCC: 21220232024 ISSCC: 32024 VLSI: 22024 JSSC: 12024 A-SSCC: 2820242025 ISSCC: 32025 VLSI: 12025 JSSC: 52025 CICC: 12025 A-SSCC: 21220252026 ISSCC: 22026 JSSC: 132026
ISSCCVLSIJSSCCICCA-SSCC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC42332
VLSI1121–
JSSC67151
CICC–––1–
A-SSCC1222–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1141212.44韓国Korea #2 · 世界World #7
VLSI Tier 1543.18韓国Korea #2 · 世界World #14
JSSC Tier 12074.95韓国Korea #2 · 世界World #9
CICC Tier 2100.36韓国Korea #2 · 世界World #22
A-SSCC Tier 2732.29韓国Korea #2 · 世界World #4
ESSERC Tier 2000.00–

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. ISSCC
    2026
    15.9 A 48Gb/s 24Gb GDDR7 DRAM for Mid-Range Inference AI with Symmetric 2CH-Mode Operation, Clock-Path Optimization, and RAS Features
    DOI
    Hyunsu Park, Sungkwon Lee, Kyunghoon Kim, Jinyoup Cha, Hyeongjun Ko, Jaehyeok Yang, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Jiseok Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Seulgi Kim, Eunji Song, Junghwan Ji, Byungjun Kang, Boram Kim, Sangyeon Byeon, Hankyu Chi, Hyungsoo Kim, Jonghwan Kim
    SK hynix
  2. ISSCC
    2026
    A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode
    DOI
    Jungtaek You, Mino Kim, Daehan Kwon, Sangsic Yoon, Joonhong Park, Hyungrok Do, Jeongje Park, Yooseok Jung, Seongseop Lee, Kyuyoung Kim, Hyeongsoo Jeong, Jaeyeol Kang, Hanbyeol Kwon, Minwook Oh, Jieun Kim, Jinseok Oh, Gi-Moon Hong, Dongyoon Ka, Seungho Lee, Heewoong Song, Minchang Kim, Daeho Yun, Sooncheol Kwon, Dongbeom Lee, Taekyun Shin, Jongmyeong Lee, Jungmin Yoon, Kyeongpil Kang, Sanghyuk Heo, Dongkyun Kim, Jieun Jang, Hyungsoo Kim
    SK hynix
  3. JSSC
    2026
    A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS
    DOI
    DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho
    Marvell · Marvell · Korea Advanced Institute of Science and Technology · SK Group (United States) · SK hynix
  4. A-SSCC
    2025
    A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver with Background Adaptive Crosstalk Equalizer
    DOI
    DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho
    Korea Advanced Institute of Science and Technology · SK hynix
  5. A-SSCC
    2025
    An 18.4Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using 4-Phase Hybrid Timing Alignment and Dual Equalization in 1b-nm DRAM Technology
    DOI
    Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim
    SK hynix · Seoul National University
  6. CICC
    2025
    A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation
    DOI
    Hyun-Seok Choi, Sunki Cho, Sanghee Lee, Hyeri Roh, Jeong-Eun Song, Honggyoo Ahn, Jihee Kim, Minchang Kim, Hankyu Chi, Deog-Kyoon Jeong, Woo-Seok Choi
    Seoul National University · SK hynix
  7. ISSCC
    2025
    22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces
    DOI
    Boram Kim, Hankyu Chi, Hyeongjun Ko, Sangyeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jinyoup Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
    SK hynix · Seoul National University
  8. ISSCC
    2025
    30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681\mu\mathrm{m}$ 1T-1MTJ Cross-Point Cell
    DOI
    Kosuke Hatsuda, Katsuhiko Hoya, Ryousuke Takizawa, Fumiyoshi Matsuoka, Takaya Yasuda, Akira Katayama, Tadashi Miyakawa, Kazuyo Senju, Kazuki Okawa, Yuka Furukawa, Yu Shimada, Katsuya Kotake, Sayaka Hirokawa, Min Chul Shin, Dong Keun Kim, Tae Ho Kim, Kyunghoon Kim, Hisanori Aikawa, Jeonghwan Song, Toshihiko Nagase, Soo Man Seo, Soo Gil Kim, Seon Yong Cha
    キオクシアKioxia · SK hynix
  9. ISSCC
    2025
    A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput
    DOI
    Wanik Cho, Chanhui Jeong, Jongwoo Kim, Jongseok Jung, Keunseon Ahn, Jayoon Goo, Sangkyu Lee, Kayoung Cho, Tei Cho, Dauni Kim, Gwan Park, Yushin Ahn, Sooyeol Chai, Gwihan Ko, Sunyoung Jung, Eunwoo Jo, Taehun Park, Jinhyun Ban, Cheoljoong Park, Jae Hyun Park, Sanghoon Oh, Sojin Jeong, Youngjun Kwak, Kyungsoo Jeong, Jinyeop Kim, Minchol Shin, Eunho Yang, Taisik Shin, Youngil Kim, Jiseong Mun, Chanyang Ryu, Huihyeon Park, Changwan Ha, Jong Tai Park, Peng Zhang, Sooyong Park, Rezaul Haque, Hang Tian, Sunghwa Ok, Wonbeom Choi, Junyoun Lim, Dongkyu Yoon, Sechun Park, Wonsun Park, Kichang Gwon, Seungpil Lee, Hwang Huh, Woopyo Jeong, Jungdal Choi
    SK hynix · SK Group (United States)
  10. JSSC
    2025
    100–112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology
    DOI
    Eunji Song, Jeonghyu Yang, Youngmin Oh, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han
    SK Group (United States) · SK hynix · Hanyang University · Samsung
  11. JSSC
    2025
    A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology
    DOI
    Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo
    SK hynix · Hanyang University · Korea Electronics Technology Institute · Samsung · Gachon University · Seoul National University · Yonsei University
  12. JSSC
    2025
    A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications
    DOI
    Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim
    Korea University · SK hynix
  13. JSSC
    2025
    An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface With On-Chip Quantized Time-Domain Feature Extraction
    DOI
    You Jang Pyeon, Jeonghoon Cho, Geonjun Choi, Junyeong Yeom, Hyunjoong Kim, Sanghyeon Cho, Yonggi Kim, Taejung Kim, Jong-Hyun Kwak, Wootaek Cho, Woojae Jeong, Myeong Woo Kim, Yunsik Lee, Heungjoo Shin, Hoon Eui Jeong, Jae Joon Kim
    Ulsan National Institute of Science and Technology · SK hynix
  14. JSSC
    2025
    An Indirect ToF Sensor With In-Pixel Adaptive ΔΣ -Scheme for Background Light Rejection and Floating Diffusion Mismatch Cancellation
    DOI
    Yongjae Park, Jubin Kang, Dahwan Park, Jung-Hye Hwang, Seonghyeok Park, Insang Son, Seong-Jin Kim
    Ulsan National Institute of Science and Technology · SK hynix · Solid (South Korea)
  15. VLSI
    2025
    Driving Innovation in DRAM Technology — Towards a Sustainable Future
    DOI
    Seon Yong Cha
    SK hynix
  16. A-SSCC
    2024
    A 1.27-mW Battery-Powered Multimodal Biosensor Interface IC for Wireless Motion Intention Recognition in Wearable Robots
    DOI
    Jimin Koo, Haidam Choi, Yoontae Jung, Ji-Hoon Suh, Sein Oh, Changhun Seok, Yegeun Kim, Injun Choi, Heewon Choee, Sunglim Han, Jiho Chun, Hoyong Seong, Sohmyung Ha, Minkyu Je
    Korea Advanced Institute of Science and Technology · Samsung · SK hynix · New York University Abu Dhabi
  17. A-SSCC
    2024
    A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology
    DOI
    Hong-Seok Choi, Jae-Geon Lee, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyung-Rok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Min-Seong Choo
    SK hynix · Hanyang University · Korea Electronics Technology Institute · Samsung · University of Suwon · Seoul National University
  18. ISSCC
    2024
    13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry
    DOI
    Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jinyoup Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sangyeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim
    SK hynix
  19. ISSCC
    2024
    13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization
    DOI
    Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Changki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim
    SK hynix
  20. ISSCC
    2024
    13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction
    DOI
    Yangho Seo, Jihee Choi, Sunki Cho, Hyunwook Han, Wonjong Kim, Gyeongha Ryu, Jungil Ahn, Younga Cho, Sungphil Choi, Seohee Lee, Wooju Lee, Chaehyuk Lee, Kiup Kim, Seongseop Lee, Sangbeom Park, Minjun Choi, Sungwoo Lee, Mino Kim, Taekyun Shin, Hyeongsoo Jeong, Hyunseung Kim, Houk Song, Yunsuk Hong, Seokju Yoon, Giwook Park, Hokeun You, Changkyu Choi, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
    SK hynix
  21. JSSC
    2024
    A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links
    DOI
    Woohyun Kwon, Hyosup Won, Taeho Kim, Sejun Jeon, Soon-Won Kwon, Ha-Il Song, Hanho Choi, Bong-Jin Kim, Huxian Jin, Jun-Gi Jo, Woosang Han, Tai-Young Kim, Gain Kim, Jake Eu, Jinho Park, Hyeon-Min Bae
    Samsung · SK hynix · Daegu Gyeongbuk Institute of Science and Technology · Korea Advanced Institute of Science and Technology
  22. VLSI
    2024
    A 336 x 240 Backside-Illuminated 3D-Stacked 7μm SPAD for LiDAR Sensor with PDE 28% at 940nm and under 0.4% Depth Accuracy Up to 10m
    DOI
    Jaehyung Jang, Jongchae Kim, Sunho Oh, Kyungsu Byun, Dahwan Park, Jihee Han, Hanseung Lee, Suhyun Yi, Hoonmoo Choi, Jongeun Kim, Namil Kim, Yongtae Gim, Minkyu Kim, Sangyoung Lee, Hansang Kim, Eunchang Lee, Minsang Yu, Jeongjoon Hwang, Seunghyun Yoon, Kwang Hwangbo, Heesang Kim, Ahyoung Cho, Taejun Baek, Sooyoung Park, Kwangjun Cho, Wonje Park, Kyung-do Kim, Hoesam Jeong, Hoon-sang Oh, Chang-rock Song
    SK hynix
  23. VLSI
    2024
    Cost-Effective LLM Accelerator Using Processing in Memory Technology
    DOI
    Hyungdeok Lee, Guhyun Kim, Dayeon Yun, Ilkon Kim, Yongkee Kwon, Euicheol Lim
    SK hynix
  24. A-SSCC
    2023
    A $\mathbf{160}\times \mathbf{120}$ Indirect Time-of-Flight Sensor with Pixel-Level Adaptive $\Delta\Sigma$-Operations for Background Light Cancellation
    DOI
    Yongjae Park, Jubin Kang, Dahwan Park, Insang Son, Jung-Hye Hwang, Seong-Jin Kim
    Ulsan National Institute of Science and Technology · SK hynix
  25. A-SSCC
    2023
    A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge
    DOI
    Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong
    Seoul National University · SK hynix
  26. ISSCC
    2023
    28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $\mathsf{i}$
    DOI
    Bvunarvul Kim, Seungpil Lee, Beomseok Hah, Kanawoo Park, Yongsoon Park, Kangwook Jo, Yujong Noh, Hyeoncheon Seol, Hyunsoo Lee, Jaehyeon Shin, Seongjin Choi, Youngdon Jung, Sungho Ahn, Yonghun Park, Sujeong Oh, Myungsu Kim, Seonauk Kim, Hyunwook Park, Taeho Lee, Haeun Won, Minsung Kim, Cheulhee Koo, Yeonjoo Choi, Suyoung Choi, Sechun Park, Dongkyu Youn, Junyoun Lim, Wonsun Park, Hwang Hur, Kichang Kwean, Hongsok Choi, Woopyo Jeong, Sungyong Chung, Jungdal Choi, Seonyong Cha
    SK hynix
  27. ISSCC
    2023
    A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement
    DOI
    Woongrae Kim, Chulmoon Jung, Seongnyuh Yoo, Duckhwa Hong, Jeongjin Hwang, Jungmin Yoon, Ohyong Jung, Joonwoo Choi, Sanga Hyun, Mankeun Kang, Sangho Lee, Dohong Kim, Sanghyun Ku, Donhyun Choi, Nogeun Joo, Sangwoo Yoon, Junseok Noh, Byeongyong Go, Cheolhoe Kim, Sunil Hwang, Mihyun Hwang, Seol-Min Yi, Hyungmin Kim, Sanghyuk Heo, Yeonsu Jang, Kyoungchul Jang, Shinho Chu, Yoonna Oh, Kwidong Kim, Junghyun Kim, Soohwan Kim, Jeongtae Hwang, Sangil Park, Junphyo Lee, Inchul Jeong, Joohwan Cho, Jonghwan Kim
    SK hynix
  28. JSSC
    2023
    A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
    DOI
    Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Jihwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Taesik Yun, Young Jun Koo, Jae-Seung Lee, Byung-Kuk Yoon, Young-Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Jung-Hyun Shin, Yeonho Lee, Jieun Jang, Joohwan Cho
    SK hynix
  29. JSSC
    2023
    A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application
    DOI
    Daehan Kwon, Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gi-Moon Hong, Dongyoon Ka, Kyudong Hwang, Jeongje Park, Kyeongpil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Vladimir Kornijcuk, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, Byeongju An, Jaewook Lee, Donguc Ko, Younggun Jun, Ilwoong Kim, Choungki Song, Ilkon Kim, Chanwook Park, Seho Kim, Chunseok Jeong, Euicheol Lim, Dongkyun Kim, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho
    SK Group (United States) · SK hynix
  30. JSSC
    2023
    A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces
    DOI
    Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim
    Korea University · SK hynix
  31. JSSC
    2023
    A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces
    DOI
    Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim
    Korea University · SK hynix
  32. JSSC
    2023
    A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
    DOI
    Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
    Seoul National University · Korea Electronics Technology Institute · Yonsei University · SK hynix
  33. JSSC
    2023
    A Pixelated Monolithic CMOS PPG Sensor for Spatial Feature Acquisition
    DOI
    Soo-Hun Kim, Seong-Min Ko, Dong-Woo Jee
    SK hynix · Ajou University
  34. JSSC
    2023
    A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM
    DOI
    Yeonwook Jung, Seongseop Lee, Hyojun Kim, Seonghwan Cho
    Korea Advanced Institute of Science and Technology · Samsung · SK hynix · Korea Aerospace Research Institute
  35. VLSI
    2023
    A 93.5%-Efficiency 13.56-MHz-Bandwidth Optimal On/Off Tracking Active Rectifier with Fully Digital Feedback-Based Delay Control for Adaptive Efficiency Compensation
    DOI
    Jisan Ahn, Hyun-Su Lee, Kyeongho Eom, Woojoong Jung, Hyung-Min Lee
    Korea University · SK hynix
  36. A-SSCC
    2022
    A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test
    DOI
    Chan-Ho Kye, Jihee Kim, Kyungmin Baek, Kahyun Kim, Sangjin Pack, Changwon Jung, Deog-Kyoon Jeong
    École Polytechnique Fédérale de Lausanne · Seoul National University · SK hynix
  37. ISSCC
    2022
    A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density
    DOI
    Wanik Cho, Jongseok Jung, Jongwoo Kim, Junghoon Ham, Sangkyu Lee, Yujong Noh, Dauni Kim, Wanseob Lee, Kayoung Cho, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Eunwoo Jo, Hanna Cho, Jong-Seok Kim, Chankeun Kwon, Cheolioona Park, Hveonsu Nam, Haeun Won, Taeho Kim, Kyeonghwan Park, Sanghoon Oh, Jinhyun Ban, Junyoung Park, Jaehyeon Shin, Taisik Shin, Junseo Jang, Jiseong Mun, Jehyun Choi, Hyunseung Choi, Suna-Wook Choi, Wonsun Park, Dongkvu Yoon, Minsu Kim, Junvoun Lim, Chiwook An, Hyunyoung Shirr, Haesoon Oh, Haechan Park, Sungbo Shim, Hwang Huh, Honasok Choi, Seungpil Lee, Jaesuna Sim, Kichana Gwon, Jumsoo Kim, Woopyo Jeong, Jungdal Choi, Kyo-Won Jin
    SK hynix
  38. ISSCC
    2022
    A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
    DOI
    Myeong-Jae Park, Ho Sung Cho, Tae-Sik Yun, Sangjin Byeon, Young Jun Koo, Sangsic Yoon, Dong Uk Lee, Seokwoo Choi, Jihwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung-Kuk Yoon, Young-Jun Park, Sang-muk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Seung Geun Baek, Kyo Yun Lee, Sang Hun Lee, Woo Sung We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seung Min Yang, Gunho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong-Yeol Lee, Su-Hyun Oh, Taejin Hwang, Junghyun Shin, Yunho Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, Junhyun Chun, Joohwan Cho
    SK hynix
  39. ISSCC
    2022
    A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications
    DOI
    Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyudong Hwang, Jeongje Park, Kyeongpil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Jaewook Lee, Donguc Ko, Younggun Jun, Keewon Cho, Ilwoong Kim, Choungki Song, Chunseok Jeong, Daehan Kwon, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho
    SK hynix
  40. ISSCC
    2022
    A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter
    DOI
    Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho
    Samsung · SK hynix · Korea Aerospace Research Institute · Korea Advanced Institute of Science and Technology
  41. JSSC
    2022
    A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer
    DOI
    Dongsuk Kang, Jae-Woo Park, Injae Park, Min-Su Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun
    Georgia Institute of Technology · Sungkyunkwan University · SK hynix
  42. JSSC
    2022
    A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
    DOI
    Ji-Hyo Kang, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gangsik Lee, Sangyeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seonyong Cha
    SK hynix · Kwangwoon University
  43. JSSC
    2022
    A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques
    DOI
    Jeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Younghwan Choo, Ji-Seon Paek, Hyun-Sik Kim
    Korea Advanced Institute of Science and Technology · Samsung · SK hynix
  44. JSSC
    2022
    A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
    DOI
    Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong
    Seoul National University · SK hynix
  45. JSSC
    2022
    An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process
    DOI
    Minsu Kim, Muqing Liu, Luke R. Everson, Chris H. Kim
    University of Minnesota · SK hynix · Western Digital · Broadcom
  46. JSSC
    2022
    Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
    DOI
    Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
    Korea Electronics Technology Institute · SK hynix · Yonsei University · Seoul National University
  47. VLSI
    2022
    0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link
    DOI
    Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
    Seoul National University · SK hynix · Samsung