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大学University · アメリカUSA · 2022–2026 LIVE

Stanford University

アメリカUSA 8位 (23 pt) · 世界World 25位 (0 pt) · 対象論文Papers 43

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0246810122022 ISSCC: 12022 VLSI: 32022 JSSC: 42022 CICC: 12022 ESSERC: 11020222023 ISSCC: 22023 VLSI: 12023 JSSC: 22023 ESSERC: 1620232024 ISSCC: 12024 VLSI: 42024 JSSC: 42024 ESSERC: 11020242025 ISSCC: 22025 VLSI: 12025 JSSC: 52025 CICC: 22025 A-SSCC: 11120252026 ISSCC: 12026 VLSI: 22026 JSSC: 12026 CICC: 262026
ISSCCVLSIJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC12121
VLSI31412
JSSC42451
CICC1––22
A-SSCC–––1–
ESSERC111––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1755.42アメリカUSA #11 · 世界World #40
VLSI Tier 11186.39アメリカUSA #2 · 世界World #16
JSSC Tier 116119.53アメリカUSA #9 · 世界World #42
CICC Tier 2533.65アメリカUSA #12 · 世界World #42
A-SSCC Tier 2111.00アメリカUSA #7 · 世界World #71
ESSERC Tier 2332.45アメリカUSA #13 · 世界World #53

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A 64.5 TFLOPS/W 16-nm AI Training Accelerator with 4T-eDRAM for Efficient Gradient and Activation Handling
    DOI
    Nestor Cuevas, Thierry Tambe, Sai Qian Zhang, David Brooks, Gu-Yeon Wei
    Harvard University · Stanford University · New York University
  2. CICC
    2026
    Fractional-N PLL–Based Micro-Oven Control for Ultra-Stable MEMS Frequency References
    DOI
    Karim Elmeligy, Rakibul Islam, Jintark Kim, Mohamed Badr Younis, Jie Yan, Jiawei Yang, Gabrielle Vukasin, Hyun-Keun Kwon, Thomas W. Kenny, Gaurav Bahl, Pavan Kumar Hanumolu
    University of Illinois Urbana-Champaign · Stanford University
  3. ISSCC
    2026
    31.9 Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW
    DOI
    Ben Keller, Rangharajan Venkatesan, Steve Dai, Jason Clemons, Matthew Fojtik, Muya Chang, Thierry Tambe, Nathaniel Pinckney, Stephen G. Tell, Qijing Huang, Shalini De Mello, Brucek Khailany
    NVIDIA · Stanford University
  4. JSSC
    2026
    Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications
    DOI
    Kalhan Koul, Olivia Hsu, Yuchen Mei, Sai Gautham Ravipati, Maxwell Strange, Jackson Melchert, Alex Carsello, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Zhouhua Xie, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
    Stanford University · University of Southern California · Massachusetts Institute of Technology
  5. VLSI
    2026
    Filter-Free Time-Gated Fluorescence CMOS Biochip with Fast Thermal Cycling for PoC DNA Testing
    DOI
    Nicholas Vitale, Mark McDermott, Davood Zare, Arjang Hassibi, Tom Lee
    Stanford University
  6. VLSI
    2026
    µAgent: A 7nm 404.3mJ/Action Edge SoC for Agentic AI Reasoning with Adaptive Block-Wise Mixed-Format 4-Bit Quantization and Decoupled Access-Execute
    DOI
    Wonsuk Jang, Christian Kubicka, Allen Pan, Pullabhatla Smriti, Win-San Khwa, Meng-Fan Chang, Priyanka Raina, Thierry Tambe
    Stanford University · TSMC
  7. A-SSCC
    2025
    Birch: A Real-Time Accelerator for Multi-Task Mixed-Domain Extended Reality Perception Workloads
    DOI
    Kathleen Feng, Kai Bartolone, Kartik Prabhu, Brianna McColm, Xingyu Ni, Siddhant Gupta, Priyanka Raina
    Stanford University
  8. CICC
    2025
    Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads
    DOI
    Kathleen Feng, Kartik Prabhu, Kai Bartolone, Jeffrey Yu, Priyanka Raina
    Stanford University
  9. CICC
    2025
    Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications
    DOI
    Po-Han Chen, Bo Wun Cheng, Michael Oduoza, Zhouhua Xie, Kalhan Koul, Sai Gautham Ravipati, Yuchen Mei, Rupert Lu, Alex Carsello, Mark Horowitz, Priyanka Raina
    Stanford University
  10. ISSCC
    2025
    15.2 A 1024-Channel 0.00029mm 2 /ch 74nW/ch Online Spatial Spike-Sorting Chip with Event-Driven Spike Detection and Self-Organizing Map Clustering
    DOI
    Arash Akhoundi, Yawende Landbrug, Pumiao Yan, E. J. Chichilnisky, Boris Murmann, Dante Gabriel Muratore
    Delft University of Technology · Stanford University · University of Hawaiʻi at Mānoa · University of Hawaii System
  11. ISSCC
    2025
    Skin-Inspired Electronics: An Emerging Sensing and Computing Platform
    DOI
    Margherita Ronchini, Weichen Wang, Yuya Nishio, Yating Yao, Zhenan Bao
    Stanford University
  12. JSSC
    2025
    A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Detection and Spatial Clustering
    DOI
    Arash Akhoundi, Pumiao Yan, Yawende Landbrug, Madeline Hays, Boris Murmann, E. J. Chichilnisky, Dante G. Muratore
    Delft University of Technology · Stanford University · University of Hawaiʻi at Mānoa
  13. JSSC
    2025
    A W-Band TX/RX Chipset With 2.4-GHz LO Synchronization Enabling Full Scalability for FMCW Radar
    DOI
    Jingzhi Zhang, Sherif S. Ahmed, Amin Arbabian
    Stanford University
  14. JSSC
    2025
    An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth
    DOI
    Junghyun Yoon, MoonHyung Jang, Changuk Lee, Yong Lim, Youngcheol Chae
    Yonsei University · Stanford University · University of California, Berkeley · Samsung
  15. JSSC
    2025
    MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator
    DOI
    Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC
  16. JSSC
    2025
    Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET
    DOI
    Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
    ETH Zurich · Integrated Systems Laboratory · University of Bologna · Stanford University
  17. VLSI
    2025
    A 1 ppb MEMS Oscillator Achieving -90 dBc/Hz at 10 Hz Offset Enabled by 5 M $\Omega$ TIA and 360° Phase Shifter
    DOI
    Rakibul Islam, Ji Shi, Ahmed Abdelrahman, Jintark Kim, Karim Elmeligy, Yongxin Li, Mohamed O. Selim, Jie Yan, Mohamed B. Younis, Ruhao Xia, Mohamed S. Aly, Mahmoud A. Khalil, Ahmed E. Hegazi, Hyun-Keun Kwon, Gabrielle Vukasin, Saurabh Saxena, Thomas W. Kenny, Gaurav Bahl, Pavan Kumar Hanumolu
    University of Illinois Urbana-Champaign · Stanford University
  18. ESSERC
    2024
    A 3.25 GHz Large-Integer Extended GCD Accelerator in 12 nm
    DOI
    Kavya Sreedhar, Gedeon Nyengele, Mark Horowitz, Christopher Torng
    Stanford University · University of Southern California
  19. ISSCC
    2024
    6.1 12Mb/s 4×4 Ultrasound MIMO Relay with Wireless Power and Communication for Neural Interfaces
    DOI
    Ernest So, Amin Arbabian
    Stanford University
  20. JSSC
    2024
    A 1024-Channel 268-nW/Pixel 36×36 μm 2 /Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces
    DOI
    Moonhyung Jang, Maddy Hays, Wei-Han Yu, Changuk Lee, Pietro Caragiulo, Athanasios T. Ramkaj, Pingyu Wang, A. J. Phillips, Nicholas Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore
    Stanford University · University of Macau · University of California, Berkeley · Yonsei University · Delft University of Technology
  21. JSSC
    2024
    A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
    DOI
    Li Wang, Zhao Zhang, Can Wang, Rehan Azmat, Weimin Shi, C. Patrick Yue
    Hong Kong University of Science and Technology · Chinese Academy of Sciences · Stanford University · Chongqing University
  22. JSSC
    2024
    Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
    DOI
    Kathleen Feng, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zach A. Myers, Brandon D’Agostino, Pranil Joshi, Stephen Richardson, Christopher Torng, Mark Horowitz, Priyanka Raina
    Stanford University
  23. JSSC
    2024
    EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
    DOI
    Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina
    Stanford University · TSMC
  24. VLSI
    2024
    MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating
    DOI
    Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC
  25. VLSI
    2024
    Medusa: A 0.83/4.6 ${\mu}\mathrm{J}$/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS
    DOI
    Rohan Doshi, Massimo Giordano, Justin Olah, Zhidong Cao, MoonHyung Jang, Luke R. Upton, Athanasios Ramkaj, Boris Murmann
    Stanford University
  26. VLSI
    2024
    Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
    DOI
    Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
    ETH Zurich · Stanford University · University of Bologna
  27. VLSI
    2024
    Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications
    DOI
    Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
    Stanford University · University of Southern California · Massachusetts Institute of Technology
  28. ESSERC
    2023
    EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry
    DOI
    Luke R. Upton, Akash Levy, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann
    Stanford University · TSMC
  29. ISSCC
    2023
    18.1 A W-Band Transceiver Array with 2.4GHz LO Synchronization Enabling Full Scalability for FMCW Radar
    DOI
    Jingzhi Zhang, Ajay Singhvi, Sherif S. Ahmed, Amin Arbabian
    Stanford University
  30. ISSCC
    2023
    27.4 Inverse Designed, Densely Integrated Classical and Quantum Photonics
    DOI
    Jelena Vuckovic, Geun Ho Ahn, Kasper Van Gasse, Melissa Guidry, Hyounghan Kwon, Jesse Lu, Daniil Lukin, Alexander Piggott, Neil Sapra, Logan Su, Jinhie Skarda, Rahul Trivedi, Dries Vercruysse, Alexander White, Joshua Yang, Kiyoul Yang
    Stanford University
  31. JSSC
    2023
    A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer
    DOI
    Stephen Weinreich, Boris Murmann
    Analog Devices · Stanford University
  32. JSSC
    2023
    Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Applications in a Zero-Change 45-nm CMOS-SOI Process
    DOI
    Panagiotis Zarkos, Sidney Buchbinder, Christos Adamopoulos, Sarika Madhvapathy, Olivia Hsu, Jake Whinnery, Pavan Bhargava, Vladimir Stojanović
    Lawrence Berkeley National Laboratory · University of California, Berkeley · Ayar Labs (United States) · Stanford University
  33. VLSI
    2023
    A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces
    DOI
    MoonHyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E.J. Chichilnisky, Boris Murmann, Dante G. Muratore
    Stanford University · University of Macau · Yonsei University · Delft University of Technology
  34. CICC
    2022
    An energy-harvesting stamp-sized reader for distance-immune interrogation of passive wireless sensors
    DOI
    Siavash Kananian, Cheng Chen, Ada S. Y. Poon
    Stanford University
  35. ESSERC
    2022
    A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS
    DOI
    Pietro Caragiulo, Athanasios Ramkaj, Amin Arbabian, Boris Murmann
    Stanford University
  36. ISSCC
    2022
    An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air Interface
    DOI
    Ajay Singhvi, Aidan Fitzpatrick, Amin Arbabian
    Stanford University
  37. JSSC
    2022
    An RF-Ultrasound Relay for Adaptive Wireless Powering Across Tissue Interfaces
    DOI
    Ernest So, Pyungwoo Yeon, E. J. Chichilnisky, Amin Arbabian
    Stanford University
  38. JSSC
    2022
    Analysis and Design of High-Harmonic-Rejection Multi-Ratio mm-Wave Frequency Multipliers
    DOI
    Jingzhi Zhang, Yu Peng, Kai Kang
    University of Electronic Science and Technology of China · Stanford University
  39. JSSC
    2022
    CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference
    DOI
    Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guenole Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC · Meta
  40. JSSC
    2022
    Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging
    DOI
    Christopher Sutardja, Ajay Singhvi, Aidan Fitzpatrick, Andreia Cathelin, Amin Arbabian
    Stanford University · STMicroelectronics
  41. VLSI
    2022
    A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET
    DOI
    Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier
    Stanford University · KU Leuven · Analog Devices
  42. VLSI
    2022
    A 90-μW Penny-Sized 1.2-gram Wireless EEG Recorder with 12-Channel FDMA Transmitter for Month-Long Continuous Mental Health Monitoring
    DOI
    Cheng Chen, Joonseok Yang, Hui Wang, Zhidong Cao, Siavash Kananian, Kevin Chen, Ada S. Y. Poon
    Stanford University · Qualcomm
  43. VLSI
    2022
    Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
    DOI
    Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina
    Stanford University