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ESSERC · 2022–2026 LIVE

Tsinghua University

対象論文Papers 24 · 筆頭著者first author 18 · 著者按分fractional 16.84 · 中国China #1 · 世界World #1

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Lu Jie ORCID6
1Wei Deng ORCID6
3Baoyong Chi ORCID4
3Haikun Jia ORCID4
3Huazhong Yang ORCID4
3Nan Sun ORCID4
7Hongyang Jia ORCID3
7Hongzhuo Liu ORCID3
7Yi Zhong3
7Yifan He ORCID3
7Yongpan Liu ORCID3
7Zhihua Wang ORCID3
13Fule Li ORCID2
13Mingyang Gu ORCID2
13Peng Wang2
13Shiyan Sun2
13Xueqing Li ORCID2
13Yan Lu ORCID2
13Yaning Wang2
20Angxiao Yan ORCID1
20Bin Gao ORCID1
20Chaoyang Xing ORCID1
20Chen Jiang ORCID1
20Chengyu Huang ORCID1
20Dong Wu1
20Dongze Li1
20Fei Qiao1
20Guo Wei ORCID1
20He Qian1
20Hongsu Wang1
20Hongtao Zhong1
20Huaqiang Wu ORCID1
20Jiajie Tang1
20Jianshi Tang ORCID1
20Junyan Lin1
20Junyang Yin ORCID1
20Lei Zhang ORCID1
20Lu Zhang1
20Luchang Lei ORCID1
20Maimaiti Nazhamaiti1
20Peng Yao1
20Qi Wei1
20Qingtian Zhang1
20Qiumeng Wei1
20Qixiu Wu ORCID1
20Ruiheng Qiu1
20Shiwei Zhang ORCID1
20Shouqing Fu ORCID1
20Shuyang Li ORCID1
20Sihao Chen ORCID1
20Sining Pan ORCID1
20Siyao Yang1
20Songming Yu1
20Taixin Li1
20Weihuang Jiang1
20Wenbin Jia1
20Wenhua Chen ORCID1
20Wenxun Wang ORCID1
20Wenyu Sun ORCID1
20Woogeun Rhee ORCID1
20Xiang Li1
20Xinhang Zou1
20Xintao Li1
20Xinyuan Lin ORCID1
20Xiyu He ORCID1
20Xun Bao ORCID1
20Yan Wang ORCID1
20Yaolei Li ORCID1
20Yaqian Sun ORCID1
20Yihang Cheng ORCID1
20Yixuan Xie1
20Yong Chen ORCID1
20Yunsong Tao ORCID1
20Yunzhao Nie ORCID1
20Zelong Chen1
20Zhonghao Chen1
20Ziyuan Guo1

対象論文Papers

  1. ESSERC
    2025
    A $25-31-\text{GHz} 0.98-\text{mW}$ Dual-Ellipse Vector-Summing Variable-Gain Phase Shifter With Current-Reusing Enabling Calibration-Free Orthogonal Phase and Gain Control
    DOI
    Zhe Zhang, Pingda Guan, Apisak Worapishet, Wei Deng, R. Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin · Mahanakorn University of Technology · Tsinghua University
  2. ESSERC
    2025
    A 11.3-to-14.1 GHz Voltage-Domain Noise-Shaping Fractional-N Digital PLL
    DOI
    Yaqian Sun, Wei Deng, Haikun Jia, Angxiao Yan, Hongzhuo Liu, Junyang Yin, Baoyong Chi
    Tsinghua University
  3. ESSERC
    2025
    A 12b 1GS/s SAR-Assisted Pipelined ADC with Gain-Error-Cancelled Dual-Path Amplifier and Partially Look-Ahead Parallel Quantization
    DOI
    Peng Wang, Yaning Wang, Lu Jie, Fule Li, Zhihua Wang
    Tsinghua University
  4. ESSERC
    2025
    A 28nm 51.6TOPS/W 2.22Mb/mm 2 System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-over-Logic 1T1C eDRAM
    DOI
    Zhaori Cong, Zhihang Qian, Shengzhe Yan, Zeyu Guo, Zhuoyu Dai, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Di Geng, Yongpan Liu
    Chinese Academy of Sciences · Tsinghua University
  5. ESSERC
    2025
    A 28nm 8-Bit 32-GS/s DAC Achieving > 55 dBc/> 40 dBc SFDR up to 5.2 GHz/13.6GHz Using 4-Channel NRZ Time-Interleaving with Background Calibration for Direct Digital Signal Synthesis
    DOI
    Sihao Chen, Chengyu Huang, Huazhong Yang, Xueqing Li
    Tsinghua University
  6. ESSERC
    2025
    A 3.4-μW Active Charge Balancing with Optimal-Pulse-Width-Searching Technique for Implantable Biphasic Neural Stimulators
    DOI
    Kai Cui, Junhong Yan, Zhi Li, Yan Lu, Xiaoya Fan, Yanzhao Ma
    Northwestern Polytechnical University · Tsinghua University
  7. ESSERC
    2025
    A 74-to-100 GHz High-Efficiency Power Amplifier with Interdigitated-Coupled-Four-Line-Based Matching Networks
    DOI
    Xun Bao, Weiping Wu, Zelong Chen, Yan Wang, Lei Zhang
    Tsinghua University · Hunan University
  8. ESSERC
    2025
    A Bidirectional Buck/Buck Hybrid Converter Achieving 96.3% Charging and 91.4% Discharging Peak Efficiency for Alkaline-to-Li-Ion Replacement
    DOI
    Xuan Wu, Caiyu Tong, Yan Lu, Mo Huang, Yuan Gao
    Southern University of Science and Technology · Tsinghua University · University of Macau
  9. ESSERC
    2025
    A Single-Channel 12-Bit 2GS/s 1.7GHz-ERBW Aperture-Error-Free Pipelined ADC with Flash-Embedded MDAC
    DOI
    Yaning Wang, Peng Wang, Guo Wei, Yihang Cheng, Hongsu Wang, Lu Jie, Nan Sun, Fule Li
    Tsinghua University
  10. ESSERC
    2025
    Enabling Energy-Efficient and High-Density eDRAM-LUT-Based Computing-in-Memory Using Anti-Ferroelectric Transistors
    DOI
    Hongtao Zhong, Zijie Zheng, Zhonghao Chen, Taixin Li, Zuopu Zhou, Leming Jiao, Xiaoyang Ma, Hongyang Jia, Huazhong Yang, Chen Jiang, Thomas Kämpfe, Kai Ni, Xiao Gong, Xueqing Li
    Tsinghua University · National University of Singapore · Princeton University · Fraunhofer Institute for Photonic Microsystems · University of Notre Dame
  11. ESSERC
    2024
    A 2.5mW Fully-Passive 2nd-Order Noise-Shaping Bang-Bang PLL with Adaptive DCO Gain Controller Achieving 305-fsrms Jitter and –246.3 dB FoM
    DOI
    Zijing Yuan, Yu Xin, Qianshui Yu, Wei Deng, Peiyuan Wan, Xu Liu, Zhijie Chen
    Beijing University of Technology · Tsinghua University
  12. ESSERC
    2024
    A 28 nm 0.25-0.61 mW 31-60fps Versatile SoC for Diverse Extreme Edge ML Workloads with Flexible Hetero-Fabric Dataflow Orchestration and Compute/Storage-Density-Adjustable CIM
    DOI
    Yaolei Li, Wenbin Jia, Xinyuan Lin, Songming Yu, Yifan He, Wenxun Wang, Xiang Li, Lu Zhang, Yixuan Xie, Junyan Lin, Huazhong Yang, Hongyang Jia, Jinshan Yue, Yongpan Liu
    Tsinghua University · Chinese Academy of Sciences
  13. ESSERC
    2024
    A 28 nm RRAM-Based 81.1 TOPS/mm2/bit Compute-In-Memory Macro with Uniform and Linear 64 Read Channels under 512 4-bit Inputs
    DOI
    Peng Yao, Qiumeng Wei, Dong Wu, Bin Gao, Siyao Yang, Ting-Ying Shen, Qingtian Zhang, Sining Pan, Jianshi Tang, He Qian, Lu Jie, Huaqiang Wu
    Tsinghua University
  14. ESSERC
    2024
    A 6.3 dBm 258-314 GHz Power Amplifier using a Broadband 8-way SQWL Power Combiner in 130-nm SiGe BiCMOS Technology
    DOI
    Shouqing Fu, Shuyang Li, Xingcun Li, Wenhua Chen
    Tsinghua University
  15. ESSERC
    2024
    A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, –91.9-dBc Reference Spur and –259-dB Jitter-Power FOM
    DOI
    Hongyu Ren, Yunbo Huang, Zunsong Yang, Tianle Chen, Xianghe Meng, Weiwei Yan, Weidong Zhang, Zhongmao Li, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
    Chinese Academy of Sciences · University of Macau · 東京大学The University of Tokyo · Tsinghua University
  16. ESSERC
    2024
    An eDRAM-Based In-Situ-Computing Processor for Homomorphic Encryption Evaluation on the Edge
    DOI
    Luchang Lei, Yongqing Zhu, Xinhang Zou, Yifan He, Zhou Zhang, Zhenyu Guan, Huazhong Yang, Yongpan Liu, Song Bian, Hongyang Jia
    Tsinghua University · Beihang University
  17. ESSERC
    2024
    Selfputing: A 0.57 μW @ 15 fps Vision Chip with Self-powered In-Pixel Computing and In-Memory Computing for Visual Perception on the Edge
    DOI
    Maimaiti Nazhamaiti, Weihuang Jiang, Haijin Su, Xin Hong, Xiangjun Wang, Yutong Li, Li Luo, Junkai Huang, Bo Liu, Jinshui Miao, Qi Wei, Fei Qiao
    Tsinghua University · Beijing Jiaotong University · Jinan University · Henan University of Science and Technology · University of Chinese Academy of Sciences
  18. ESSERC
    2023
    A 0.021mm2 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping
    DOI
    Chaoyang Xing, Yi Zhong, Nan Sun, Lu Jie
    Tsinghua University
  19. ESSERC
    2023
    A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors
    DOI
    Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun
    Tsinghua University
  20. ESSERC
    2023
    A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS
    DOI
    Yunzhao Nie, Woogeun Rhee, Zhihua Wang
    Tsinghua University
  21. ESSERC
    2023
    A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration
    DOI
    Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun
    Tsinghua University
  22. ESSERC
    2023
    A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers
    DOI
    Dongze Li, Wei Deng, Haikun Jia, Ruiheng Qiu, Xintao Li, Ziyuan Guo, Baoyong Chi
    Tsinghua University
  23. ESSERC
    2023
    A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter
    DOI
    Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi
    Tsinghua University
  24. ESSERC
    2022
    A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase $\text{Noise +20}\text{logN}_{\mathrm{d}\mathrm{i}\mathrm{v}}$
    DOI
    Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi
    Tsinghua University