VLSI · 2022–2026 LIVE

Tsinghua University

対象論文Papers 31 · 筆頭著者first author 26 · 著者按分fractional 24.56 · 中国China #1 · 世界World #3

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Shouyi Yin ORCID	8
1	Yang Hu ORCID	8
3	Shaojun Wei ORCID	7
4	Yang Wang ORCID	5
5	Baoyong Chi ORCID	4
5	Haikun Jia ORCID	4
5	Lu Jie ORCID	4
5	Nan Sun ORCID	4
5	Ruiqi Guo ORCID	4
5	Wei Deng ORCID	4
5	Yiqi Wang ORCID	4
5	Yongpan Liu ORCID	4
5	Zhen He	4
5	Zihan Wu	4
15	Huiming Han	3
15	Jian Zhang ORCID	3
15	Wenyu Sun ORCID	3
15	Xiaolong Yang	3
15	Yan Wang ORCID	3
15	Yubin Qin ORCID	3
15	Zhiheng Yue ORCID	3
15	Zhihua Wang ORCID	3
15	Zhiren Zhao	3
24	Angxiao Yan ORCID	2
24	Chenguang Li	2
24	Hanjun Jiang ORCID	2
24	Hongyang Jia ORCID	2
24	Huazhong Yang ORCID	2
24	Jiawen Wang	2
24	Leibo Liu ORCID	2
24	Ruitao Wang	2
24	Tiefu Li ORCID	2
24	Wei Zhu ORCID	2
24	Yi Zhong	2
24	Yifan He ORCID	2
36	Aoyang Zhang ORCID	1
36	Bin Gao ORCID	1
36	Bohan Yang ORCID	1
36	Bufan Zhu ORCID	1
36	Chao Tang	1
36	Chaoyang Xing ORCID	1
36	Chen Tang ORCID	1
36	Cheng Nian	1
36	Cheng Peng	1
36	Chenggang Zhao	1
36	Chengxiang Ma	1
36	Chun Zhang	1
36	Chunqi Qian	1
36	Cong Sun	1
36	Dazheng Deng	1
36	Dexuan Huo ORCID	1
36	Dong Wu	1
36	Dongze Li	1
36	Falong Zhou	1
36	Fasih Ud Din Farrukh	1
36	Fuzhi Xue	1
36	Guo Wei ORCID	1
36	Hanning Wang ORCID	1
36	Haotian Mao	1
36	He Qian	1
36	Heyue Li	1
36	Hong Chen ORCID	1
36	Hongzhuo Liu ORCID	1
36	Huan Qiao	1
36	Huanyu Ge	1
36	Huaqiang Wu ORCID	1
36	Jianshi Tang ORCID	1
36	Jiaqi Zhang	1
36	Jiaying Peng	1
36	Jilin Zhang ORCID	1
36	Jinshan Yue ORCID	1
36	Jun Shi	1
36	Kai Wang	1
36	Kaimeng Liu	1
36	Kun Wang	1
36	Lei Wang	1
36	Mingcheng Shi	1
36	Mingtao Zhan ORCID	1
36	Mingyu Gao ORCID	1
36	Ning Deng	1
36	Peng Yao	1
36	Renwei Chen ORCID	1
36	Ruichen Wan ORCID	1
36	Shaonan Wu	1
36	Shijie Yin	1
36	Shiyan Sun	1
36	Shuyuan Zhang ORCID	1
36	Siqi Zhang	1
36	Songchun Xu	1
36	Songming Yu	1
36	Tian Tian ORCID	1
36	W. Qixiu	1
36	Wei Chang	1
36	Weinan Chen	1
36	Wen Jia	1
36	Wenjie Yang ORCID	1
36	Wenqiang Huang ORCID	1
36	Xiangchao Ma	1
36	Xiangyu Nie	1
36	Xiaofeng Chen	1
36	Xiaorui Mo	1
36	Xiaosen Liu ORCID	1
36	Xichen Sun	1
36	Xing Wang ORCID	1
36	Xinyu Dai ORCID	1
36	Xinyuan Lin ORCID	1
36	Xizhu Chen	1
36	Xuanyan Liu	1
36	Xuchen Men	1
36	Xueqing Li ORCID	1
36	Xuliang Wang ORCID	1
36	Xurui Zhu	1
36	Yan Lu ORCID	1
36	Yaolei Li ORCID	1
36	Yichi Sun	1
36	Yifan Li ORCID	1
36	Yilin Shen	1
36	Yong Chen ORCID	1
36	Yu Fu	1
36	Yuan He	1
36	Yuanxiao Wang	1
36	Zhen Zhu	1
36	Zhewen Yu	1
36	Zhiguo Tong ORCID	1
36	Zhiqi Yang	1
36	Zhishuai Zhang ORCID	1
36	Ziheng Ma	1
36	Zongle Huang ORCID	1

対象論文Papers

VLSI
2026

A 1.5-to-20.5 GHz Intrinsic-Spurious-Rejection Real-If Dual-Translation Transceiver Chipset Achieving 10-Gb/s 1024-QAM and 5-μs Hopping
DOI
Dongze Li, Yichi Sun, Wei Deng, Xiangyu Nie, Fuzhi Xue, Haikun Jia, Liangjiang Zhou, Rui Wu, Baoyong Chi

Tsinghua University · Chinese Academy of Sciences · Aerospace Information Research Institute
VLSI
2026

A 28nm 44.15TFLOPS/W and 1.57TFLOPS/mm 2 Joint-Alignment Floating-Point CIM Macro with ISO26262 ASIL-D Safety Level for Autonomous Driving
DOI
Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Yang Hu, Fengbin Tu, Shouyi Yin

Tsinghua University · Hong Kong University of Science and Technology
VLSI
2026

A 2D-Extendable $\mathbf{4 8 V}$-1V Ladder-Series-Capacitor Buck Converter for Computing Power Delivery
DOI
Zhiguo Tong, Wenjie Yang, Zhewen Yu, Shousheng Han, Rui P. Martins, Yan Lu

Tsinghua University · University of Macau
VLSI
2026

A 45.3-To-53.9-GHz Circular-Dual-Core Series-Resonance-Harmonic-Extraction VCO Featuring Common-Mode Noise-Diversion Technique Achieving -112.5 dBc/Hz Phase Noise, Average 199.1/203.9 dBc/Hz FoM A /FoM TA and 0.8 dB Variation at 1-MHz Offset
DOI
Huanyu Ge, Haikun Jia, Wei Deng, Baoyong Chi

Tsinghua University
VLSI
2026

A 4Mb 3Bits/Cell RRAM Macro in 12nm FinFET Technology with the Smallest 0.019μm 2 Bit-Cell, 100K-Cycle Endurance and 10 Years Retention up to 125°C
DOI
Yuan He, Kaimeng Liu, Jianshi Tang, Cong Sun, Wei Chang, Chengxiang Ma, Haotian Mao, Huan Qiao, Kun Wang, Falong Zhou, Songchun Xu, Yilin Shen, Zhen Zhu, Mingcheng Shi, Xurui Zhu, Kun Wang, Xiangchao Ma, Dong Wu, Peng Yao, Bin Gao, He Qian, Huaqiang Wu

Tsinghua University
VLSI
2026

A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase Detector Achieving 53.8fs rms Jitter and −281.1dB FoM N
DOI
Yunbo Huang, Zunsong Yang, Li Wang, Kai Cheng, Hongyu Ren, Xiaoyu Shan, Pui-In Mak, Yong Chen, Bo Li

Chinese Academy of Sciences · University of Macau · Tsinghua University
VLSI
2026

A 5GS/s Staggered Working Point Ensemble TRNG with a Stochastic Model Achieving 4064.5 Mbps Entropy-Throughput and 997.6 fJ/Entropy-Bit
DOI
Shaonan Wu, Ziheng Ma, Bohan Yang, Yuanxiao Wang, Zhiqi Yang, Weinan Chen, Hanning Wang, Min Zhu, Aoyang Zhang, Leibo Liu

Tsinghua University
VLSI
2026

A Cryo-CMOS Fully-Integrated Superconducting Qubit Reflectometry Readout IC with FCNN-Based Adaptive Drift Mitigation and FIR-DSM-Based Stimulus TX
DOI
Yanshu Guo, Heyue Li, Siqi Zhang, Jun Shi, Shijie Yin, Qichun Liu, Ning Deng, Zhihua Wang, Tiefu Li, Guoxing Wang, Yuanjin Zheng, Hanjun Jiang

Shanghai Jiao Tong University · Tsinghua University · Beijing Academy of Quantum Information Sciences · Nanyang Technological University
VLSI
2026

Uni4D: A 12nm 0.16mJ/Frame 4D Gaussian Spatial Video Rendering Processor with Unified Deformation and On-Chip Hierarchical Sorting
DOI
Cheng Nian, Xiaorui Mo, Jiaqi Zhang, Jiaying Peng, Fasih Ud Din Farrukh, Yifan Li, Wen Jia, Fei Chen, Liang Lu, Chun Zhang

Tsinghua University · Research Institute of Tsinghua University in Shenzhen
VLSI
2025

A 0.0035mm 2 86dB-SNR 1.25MHz-BW Noise-Shaping SAR ADC Enabling kT/C Noise Shaping
DOI
Xing Wang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Tsinghua University
VLSI
2025

A 10W 3.8-5V Input IVR Chiplet with 93%-Peak-Efficiency and 3.2A/mm2 Density Featuring Wide Load Range and Adaptive Ganging for 2.5D/3D Vertical Power Delivery
DOI
Xichen Sun, Xuliang Wang, Renwei Chen, Xuchen Men, Junmin Jiang, Yan Wang, Xiaosen Liu

Tsinghua University · Southern University of Science and Technology
VLSI
2025

A 94.4dB-SNDR 500kHz-BW Multi-Rate MASH 0-1-0 ADC with Easy-to-Drive Capacitive Input and Deadband-Embedded Gm-C Loop Filter
DOI
Chaoyang Xing, Yi Zhong, Nan Sun, Lu Jie

Tsinghua University
VLSI
2025

A 94Hz Inference and 7.4mJ/Epoch Fine-Tune Edge SoC for Diffusion-Based Robot Manipulation with Speculation and Disturbance Enhancement
DOI
Shuyuan Zhang, Xizhu Chen, Cheng Peng, Huazhong Yang, Yongpan Liu, Hongyang Jia

Tsinghua University
VLSI
2025

A Cryogenic ${1.08mW}$/Qubit Fully-Integrated 4-Channel Frequency-Division-Multiplexing Transmon Qubit State Readout ASIC in 28nm Bulk CMOS
DOI
Wenqiang Huang, Yanshu Guo, Tian Tian, Qichun Liu, Guo Wei, Xuanyan Liu, Tiefu Li, Wen Jia, Yuanjin Zheng, Zhihua Wang, Hanjun Jiang

Tsinghua University · Nanyang Technological University · Beijing Academy of Quantum Information Sciences
VLSI
2025

An 88.8dB-SNDR 6-MS/s Pipelined SAR ADC with A Closed-Loop Dynamic Amplifier Featuring Highly-Linear Full-Scale Output Swing
DOI
Zongnan Wang, Haoyang Luo, Rongjia Bao, Lu Jie, Xiyuan Tang

Peking University · Tsinghua University
VLSI
2025

CELLA: A 28nm Compute-Memory Co-Optimized Real-Time Digital CIM-Based Edge LLM Accelerator with 1.78ms-Response in Prefill and 31.32 Token/s in Decoding
DOI
Zihan Wu, Yiqi Wang, Zhen He, Bohan Yang, Yang Wang, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin

Tsinghua University · Hong Kong University of Science and Technology
VLSI
2025

LLM-CIM: A 28nm 126.7TOPS/W Input-LUT-Based Digital CIM Macro with Reconfigurable Matrix Multiplication and Nonlinear Operation Modes for LLMs
DOI
Yiqi Wang, Zhen He, Zihan Wu, Ruiqi Guo, Longke Yan, Huiming Han, Yang Wang, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin

Tsinghua University · Hong Kong University of Science and Technology
VLSI
2024

A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System
DOI
Ruichen Wan, Wei Deng, W. Qixiu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, H. Sanming, Zhihua Wang, Baoyong Chi

Tsinghua University · Chinese Academy of Sciences · Aerospace Information Research Institute · Southeast University
VLSI
2024

A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating
DOI
Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin

Tsinghua University
VLSI
2024

A 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-Assisted Cores
DOI
Chen Tang, Xinyuan Lin, Zongle Huang, Wenyu Sun, Hongyang Jia, Yongpan Liu

Tsinghua University
VLSI
2024

A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation
DOI
Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

Tsinghua University · Hong Kong University of Science and Technology
VLSI
2024

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications
DOI
Zhuoyu Dai, Shengzhe Yan, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu

Chinese Academy of Sciences · Tsinghua University
VLSI
2024

A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication
DOI
Yubin Qin, Yang Wang, Xiaolong Yang, Zhiren Zhao, Shaojun Wei, Yang Hu, Shouyi Yin

Tsinghua University
VLSI
2024

ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction
DOI
Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin

Tsinghua University · Hong Kong University of Science and Technology
VLSI
2023

A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing
DOI
Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang

National Taiwan University · Yonsei University · The University of Texas at Austin · Tsinghua University
VLSI
2023

A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing
DOI
Yang Wang, Yubin Qin, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin

Tsinghua University
VLSI
2023

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro
DOI
Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu

Chinese Academy of Sciences · Tsinghua University
VLSI
2023

ANP-G: A 28nm 1.04pJ/SOP Sub-mm2 Spiking and Back-propagation Hybrid Neural Network Asynchronous Olfactory Processor Enabling Few-shot Class-incremental On-chip Learning
DOI
Dexuan Huo, Jilin Zhang, Xinyu Dai, Jian Zhang, Chunqi Qian, Kea-Tiong Tang, Hong Chen

Tsinghua University · National Tsing Hua University
VLSI
2023

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope
DOI
Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi

Tsinghua University
VLSI
2022

A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP
DOI
Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kai Wang, Yan Wang

Tsinghua University
VLSI
2022

An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology
DOI
Wei Zhu, Ruitao Wang, Jian Zhang, Jiawen Wang, Chenguang Li, Yan Wang

Tsinghua University