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VLSI · 2022–2026 LIVE

University of Science and Technology of China

対象論文Papers 4 · 筆頭著者first author 4 · 著者按分fractional 2.72 · 中国China #7 · 世界World #41

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Fujiang Lin ORCID2
1Weichen Tao ORCID2
1Yizhe Hu ORCID2
4Aodi Li1
4Juncheng Deng1
4Junlin Li1
4Liheng Lou1
4Lin Cheng ORCID1
4Shaoqi Yang1
4Song Wang1
4Weichen Zhao1
4Yi Kang1
4Yichao Ji ORCID1
4Yuhao Yang1
4Zhongjun Zhang1

対象論文Papers

  1. VLSI
    2025
    A 0.184mm 2 $W$-Band Single-RTWO-Based Subharmonic RX Achieving 3.72 dB-NF and I/Q Mismatch < 0.8° in 22 nm CMOS
    DOI
    Juncheng Deng, Aodi Li, Junlin Li, Weichen Tao, Shaoqi Yang, Zhongjun Zhang, Yuhao Yang, Xin Cheng, Fujiang Lin, Robert Bogdan Staszewski, Liheng Lou, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  2. VLSI
    2025
    A 16-24V to 1-1.8V 1.187W/mm3-Power-Density Hybrid DC-DC Converter Featuring Inductor Current in $\Sigma$-Fibonacci Region for Unmanned Aerial Vehicle Applications
    DOI
    Yichao Ji, Lin Cheng
    University of Science and Technology of China
  3. VLSI
    2023
    A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV
    DOI
    Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang
    University of Science and Technology of China · Xi'an UniIC Semiconductors (China) · Chinese Academy of Sciences
  4. VLSI
    2023
    An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM
    DOI
    Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu
    University of Science and Technology of China · University College Dublin