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大学University · インドIndia · 2022–2026 LIVE

Indian Institute of Technology Delhi

世界World 25位 (0 pt) · 対象論文Papers 4

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0122022 ISSCC: 12022 JSSC: 122022202320242025 ESSERC: 1120252026 JSSC: 112026
ISSCCJSSCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC1––––
JSSC1–––1
ESSERC–––1–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1100.08世界World #112
VLSI Tier 1000.00–
JSSC Tier 1211.09世界World #146
CICC Tier 2000.00–
A-SSCC Tier 2000.00–
ESSERC Tier 2111.00世界World #101

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. JSSC
    2026
    A 6.9-ppm/°C, 0.66-mV/V Line Regulation, 50-mA Multi-Loop Low-Dropout Regulator With Integrated Single-BJT Voltage and Current References
    DOI
    Raghav Bansal, Shouri Chatterjee
    Indian Institute of Technology Delhi
  2. ESSERC
    2025
    Design and Analysis of Voltage Regulators for Retimer Latches in RF NRZ DACs
    DOI
    Rakesh Kumar Palani
    Indian Institute of Technology Delhi
  3. ISSCC
    2022
    A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology
    DOI
    Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios Dogiamis, Brent Carlton, Mark Chakravorti, Stefano Pellerano, Christopher Hull
    Intel · Indian Institute of Technology Delhi
  4. JSSC
    2022
    A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET
    DOI
    Steven Callender, Abhishek Agrawal, Amy Whitcombe, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Christopher Hull, Stefano Pellerano
    Intel · Indian Institute of Technology Delhi · Amazon