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JSSC · 2022–2026 LIVE

Indian Institute of Technology Madras

対象論文Papers 7 · 筆頭著者first author 4 · 著者按分fractional 3.97 · 世界World #71

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Nagendra Krishnapura ORCID3
2Shanthi Pavan ORCID2
3Abhishek Bhat ORCID1
3Aditya Narayanan ORCID1
3Nishanth Basavaraj ORCID1
3Paramita Banerjee1
3R. Gautam ORCID1
3R. S. Ashwin Kumar ORCID1
3Sankaran Aniruddhan ORCID1
3Saurabh Saxena ORCID1

対象論文Papers

  1. JSSC
    2026
    A Self-Injection LC Oscillator for Flicker Noise Reduction
    DOI
    Bahram Jafari, Ali Ghafari, Sankaran Aniruddhan, Shahriar Mirabbasi, Sudip Shekhar
    University of British Columbia · Indian Institute of Technology Madras
  2. JSSC
    2025
    A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver
    DOI
    Chakravarti Bheemisetti, Karunanidhan Pandey, Idan Lotan, Gadi Ori, Ahmad Khairi, Yoel Krupnik, Udi Virobnik, Boyapati Subrahmanyam, Ariel Cohen, Nagendra Krishnapura
    Intel · Intel · Intel · Indian Institute of Technology Madras
  3. JSSC
    2024
    A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays
    DOI
    Aditya Narayanan, Abhishek Bhat, Nagendra Krishnapura
    Indian Institute of Technology Madras · Cisco Systems (United States)
  4. JSSC
    2024
    Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining
    DOI
    Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj
    Indian Institute of Technology Madras · Indian Institute of Technology Roorkee
  5. JSSC
    2022
    A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS
    DOI
    R. Gautam, Saurabh Saxena
    Indian Institute of Technology Madras
  6. JSSC
    2022
    Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier
    DOI
    R. S. Ashwin Kumar, Nagendra Krishnapura, Paramita Banerjee
    Indian Institute of Technology Madras · Indian Institute of Technology Kanpur
  7. JSSC
    2022
    Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs
    DOI
    Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan
    Analog Devices · MediaTek · Indian Institute of Technology Madras