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ISSCC · 2022–2026 LIVE

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対象論文Papers 7 · 筆頭著者first author 1 · 著者按分fractional 1.79 · 世界World #18

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Dmytro Cherniak4
2Christoph Wagner1
2Giacomo Castoro ORCID1
2Giovanni Steffan1
2Luca Avallone ORCID1
2Mario Motz1
2Niels Christotters1
2Saleh Karman ORCID1
2Sanaz Hadipour Abkenar1
2Soumya Krishnapuram Sireesh ORCID1
2Thorsten Brandt1
2Udo Ausserlechner ORCID1

対象論文Papers

  1. ISSCC
    2025
    34.2 A 380μW and −242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS
    DOI
    Simone Mattia Dartizio, Giacomo Castoro, Stefano Gallucci, Michele Rossoni, Riccardo Moleri, Francesco Tesolin, Pietro Salvi, Saleh Karman, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  2. ISSCC
    2024
    10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
    DOI
    Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  3. ISSCC
    2023
    23.3 A 51A Hybrid Magnetic Current Sensor with a Dual Differential DC Servo Loop and 43mArms Resolution in a 5MHz Bandwidth
    DOI
    Amirhossein Jouyaeian, Qinwen Fan, Mario Motz, Udo Ausserlechner, Kofi A. A. Makinwa
    Delft University of Technology · Infineon
  4. ISSCC
    2023
    25.4 A 4b RFDAC at 8GS/s for FMCW Chirps with 4GHz Bandwidth in $\boldsymbol{10\mu} \mathbf{s}$
    DOI
    Soumya Krishnapuram Sireesh, Sanaz Hadipour Abkenar, Niels Christotters, Christoph Wagner, Thorsten Brandt, Andreas Stelzer
    Johannes Kepler University of Linz · Infineon
  5. ISSCC
    2023
    4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  6. ISSCC
    2023
    4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  7. ISSCC
    2022
    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
    DOI
    Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua