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企業・研究機関Company / Institute · AT · 2022–2026 LIVE

Infineon

世界World 9位 (13 pt) · 対象論文Papers 48

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0510152022 ISSCC: 12022 JSSC: 72022 CICC: 12022 A-SSCC: 12022 ESSERC: 41420222023 ISSCC: 42023 JSSC: 42023 ESSERC: 31120232024 ISSCC: 12024 VLSI: 22024 JSSC: 42024 ESSERC: 31020242025 ISSCC: 12025 JSSC: 42025 ESSERC: 4920252026 VLSI: 12026 JSSC: 342026
ISSCCVLSIJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC1411–
VLSI––2–1
JSSC74443
CICC1––––
A-SSCC1––––
ESSERC4334–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1711.79世界World #18
VLSI Tier 1321.51世界World #19
JSSC Tier 12247.50世界World #8
CICC Tier 2100.23世界World #22
A-SSCC Tier 2110.50世界World #25
ESSERC Tier 21457.83世界World #2

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. JSSC
    2026
    A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication
    DOI
    Lucrezia Navarin, Karl Norling, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam, Andrea Neviani, Andrea Bevilacqua
    University of Padua · Infineon
  2. JSSC
    2026
    A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  3. JSSC
    2026
    An 80 MHz CT DSM With SMASH DAC Achieving 106.2 dB SFDR Without Linearity Calibration
    DOI
    Ahmed Abdelaal, John G. Kauffman, Matteo Dalla Longa, Francesco Conzatti, Maurits Ortmanns
    Universität Ulm · Infineon
  4. VLSI
    2026
    A Robust, Digital-Friendly, Differential and Distributed Supply Monitor Architecture for Automotive SoC in 28nm
    DOI
    Stefano Bonomi, Frank Praemassing, Sie Boo Chiang, Werner Grollitsch, Roberto Nonis
    Infineon
  5. ESSERC
    2025
    A 24-MHz BW, 97-dB SFDR, CT ΔΣ Modulator with a Jitter Robust Shunt Current Steering DAC
    DOI
    Matteo Dalla Longa, Francesco Conzatti, Alonso Morgado, Enara Ortega Garcia, Ahmed Abdelaal, John G. Kauffman, Maurits Ortmanns
    Infineon · Universität Ulm
  6. ESSERC
    2025
    A 3 MHz Calibration-Free CT-DSM Achieving 102.3dB SFDR Using MASH Dual Quantization
    DOI
    Ahmed Abdelaal, David-Peter Wiens, Matteo Dalla Longa, Jonathan Ungethüm, John G. Kauffman, Francesco Conzatti, Maurits Ortmanns
    Universität Ulm · Infineon
  7. ESSERC
    2025
    A 381.4 μW 114dB-A DR Companding VCO-ADC for MEMS Microphones Using a Multirate Architecture
    DOI
    J. Granizo, R. Garvi, R. Carrero, J. Fernandez, V. Medina, D. Straeussnigg, A. Wiesbauer, L. Hernandez
    Infineon
  8. ESSERC
    2025
    A Resonant Multi-Mode DC-DC Converter with Auto-Tuning for 2–6V Input and up to 1A Load
    DOI
    Adrian Gehl, Kyrylo Cherniak, Olga Kharko, Gianluca Marin, Frank Prämaßing, Bernhard Wicht
    Leibniz University Hannover · Infineon
  9. ISSCC
    2025
    34.2 A 380μW and −242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS
    DOI
    Simone Mattia Dartizio, Giacomo Castoro, Stefano Gallucci, Michele Rossoni, Riccardo Moleri, Francesco Tesolin, Pietro Salvi, Saleh Karman, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  10. JSSC
    2025
    A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
    DOI
    Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
    Politecnico di Milano · Infineon
  11. JSSC
    2025
    A 4-bit RFDAC-Based FMCW Modulator for Automotive Radar
    DOI
    Soumya Krishnapuram Sireesh, Niels Christoffers, Sanaz Hadipour Abkenar, Christoph Wagner, Andreas Stelzer
    Infineon · Silicon Austria Labs (Austria) · Johannes Kepler University of Linz
  12. JSSC
    2025
    A 470- μ W, 102.6-dB DR, 20-kHz BW Calibration-Free ΔΣ Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC
    DOI
    Matteo Dalla Longa, Francesco Conzatti, Omar Ismail, Ahmed Abdelaal, John G. Kauffman, Maurits Ortmanns
    Infineon · Universität Ulm
  13. JSSC
    2025
    A 78.2-dB Dynamic Range Shunt-Based Current Sensor for BLDC Motor Control With 2.75- μ s Conversion Time and 0.4-mm² Active Area
    DOI
    Antonio Aprile, Jaya Satyanarayana Yarragunta, Andreas Fugger, Francesco Conzatti, Edoardo Bonizzoni, Piero Malcovati
    University of Pavia · Infineon
  14. ESSERC
    2024
    A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs
    DOI
    Luigi Grimaldi, Agata Iesurum, Giovanni Boi, Fabio Versolatto, Giovanni Steffan, Fabio Padovan, Heorhii Koltsov, Andrea Bevilacqua, Dmytro Cherniak
    Infineon · University of Padua
  15. ESSERC
    2024
    A 75 dB DR, 0.13 μT/√Hz Hall Sensor with CT-ΣΔ-ADC, Digital Chopper Ripple Rejection Loops and Custom Nano-Timing Techniques
    DOI
    Dan-Ioan-Dumitru Stoica, Mario Motz, Andrei Gheorghe, Ilie-Ionuţ Cristea, Liviu Turică
    Infineon
  16. ESSERC
    2024
    A Cryogenic Digital-to-Analog Converter for Trapped-Ion Quantum Computing
    DOI
    Michael Sieberer
    Infineon
  17. ISSCC
    2024
    10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
    DOI
    Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  18. JSSC
    2024
    A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
    DOI
    Francesco Tesolin, Simone M. Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  19. JSSC
    2024
    A 14–32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Gianluca Brozzetti, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti
    University of Pavia · Infineon
  20. JSSC
    2024
    A 22-dBA Digital Optical MEMS Microphone
    DOI
    Niccolò de Milleri, Luca Valli, Marc Fueldner, Andreas Wiesbauer, Andrea Baschirotto
    Infineon · University of Milano-Bicocca · Infineon
  21. JSSC
    2024
    Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
    DOI
    Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
    University of Padua · Infineon
  22. VLSI
    2024
    A 470μW, 102.6dB-DR, 20kHz BW Calibration-Free $\Delta\Sigma$ Modulator with SFDR in Excess of 110dBc using an Intrinsically Linear 13-Level DAC
    DOI
    Matteo Dalla Longa, Francesco Conzatti, Omar Ismail, John G. Kauffman, Maurits Ortmanns
    Infineon · Universität Ulm
  23. VLSI
    2024
    A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
    DOI
    Riccardo Moleri, Simone Mattia Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  24. ESSERC
    2023
    A 125dBSPL 1%-THD, 115μA MEMS Microphone Using Passive Pre-Distortion Technique
    DOI
    Miodrag Nikolić, Wilfried Florian, Richard Gaggl, Lei Liao
    Infineon · Infineon
  25. ESSERC
    2023
    A 2-8V V in 670mA Scalable Multi-Ratio SC DCDC Converter for MCU Integration in 28nm CMOS Achieving 91% Peak Efficiency
    DOI
    Adrian Gehl, Kyrylo Cherniak, Olga Kharko, Gianluca Marin, Petru Bacinski, Frank Prämaßing, Bernhard Wicht
    Leibniz University Hannover · Infineon
  26. ESSERC
    2023
    A 22dBA digital optical MEMS microphone
    DOI
    Niccolò de Milleri, Andreas Wiesbauer, Andrea Baschirotto
    Infineon · University of Milano-Bicocca
  27. ISSCC
    2023
    23.3 A 51A Hybrid Magnetic Current Sensor with a Dual Differential DC Servo Loop and 43mArms Resolution in a 5MHz Bandwidth
    DOI
    Amirhossein Jouyaeian, Qinwen Fan, Mario Motz, Udo Ausserlechner, Kofi A. A. Makinwa
    Delft University of Technology · Infineon
  28. ISSCC
    2023
    25.4 A 4b RFDAC at 8GS/s for FMCW Chirps with 4GHz Bandwidth in $\boldsymbol{10\mu} \mathbf{s}$
    DOI
    Soumya Krishnapuram Sireesh, Sanaz Hadipour Abkenar, Niels Christotters, Christoph Wagner, Thorsten Brandt, Andreas Stelzer
    Johannes Kepler University of Linz · Infineon
  29. ISSCC
    2023
    4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  30. ISSCC
    2023
    4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  31. JSSC
    2023
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  32. JSSC
    2023
    A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop
    DOI
    Amirhossein Jouyaeian, Qinwen Fan, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa
    Delft University of Technology · Infineon
  33. JSSC
    2023
    A Hybrid Magnetic Current Sensor With a Multiplexed Ripple-Reduction Loop
    DOI
    Amirhossein Jouyaeian, Qinwen Fan, Roger Zamparette, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa
    Delft University of Technology · Infineon
  34. JSSC
    2023
    A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  35. A-SSCC
    2022
    Sub-GHz RF Energy Harvester including a Small Loop Antenna
    DOI
    Darshan Shetty, Christoph Steffan, Wolfgang Bosch, Jasmin Grosinger
    Infineon · Graz University of Technology
  36. CICC
    2022
    A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  37. ESSERC
    2022
    A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS
    DOI
    Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
    University of Padua · Infineon
  38. ESSERC
    2022
    A 24-30 GHz Broadband Doherty PA with a maximum 15.37 dBm Pavg and 14.6% PAEavg in 0.13 μm SiGe for 400 MHz BW 5G NR
    DOI
    Hao Gao, Sina Mortezazadeh Mahani, David Seebacher, Matteo Bassi, Gernot Hueber
    Silicon Austria Labs (Austria) · Eindhoven University of Technology · Infineon
  39. ESSERC
    2022
    A 69dBA-730µW Silicon Microphone System with Ultra & Infra-Sound Robustness
    DOI
    Jose Luis Ceballos, Christopher Rogi, Fulvio Ciciotti, Cesare Buffa, Dietmar Straeussnigg, Andreas Wiesbauer
    Infineon
  40. ESSERC
    2022
    A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti
    University of Pavia · Infineon
  41. ISSCC
    2022
    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
    DOI
    Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  42. JSSC
    2022
    A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
    DOI
    Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
    University of Padua · Lund University · Infineon
  43. JSSC
    2022
    A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
    DOI
    Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Infineon
  44. JSSC
    2022
    A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
    DOI
    Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Qualcomm · Infineon · University College Dublin
  45. JSSC
    2022
    A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
    DOI
    Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
    University of Pavia · University of Padua · Infineon
  46. JSSC
    2022
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
    DOI
    Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · Qualcomm · University of Padua
  47. JSSC
    2022
    Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
    DOI
    Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
    Infineon · Politecnico di Milano
  48. JSSC
    2022
    Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance
    DOI
    Alessandro Franceschin, Domenico Riccardi, Andrea Mazzanti
    University of Pavia · STMicroelectronics · Infineon