TopSSCS
← Infineon

JSSC · 2022–2026 LIVE

Infineon

対象論文Papers 22 · 筆頭著者first author 4 · 著者按分fractional 7.50 · 世界World #8

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Dmytro Cherniak5
2Fabio Padovan ORCID3
2Francesco Conzatti ORCID3
2Luca Avallone ORCID3
2Matteo Bassi ORCID3
6David Seebacher ORCID2
6Giovanni Steffan2
6Mario Motz2
6Matteo Dalla Longa ORCID2
6Udo Ausserlechner ORCID2
11Ahmed Abdelaal ORCID1
11Alessandro Garghetti ORCID1
11Alexander Uran1
11Andreas Fugger ORCID1
11Andreas Wiesbauer1
11Carlo Samori ORCID1
11Daniele Dal Maistro1
11Davide Manente ORCID1
11Domenico Riccardi ORCID1
11Gianluca Brozzetti1
11Giovanni Boi ORCID1
11John G. Kauffman ORCID1
11Karl Norling1
11Krithika Rathinam1
11Lorenzo Scaletti ORCID1
11Luca Valli1
11Marco Parenzan ORCID1
11Maurits Ortmanns ORCID1
11Niccolò de Milleri ORCID1
11Niels Christoffers1
11Omar Ismail ORCID1
11Saleh Karman ORCID1
11Sanaz Hadipour Abkenar1
11Simone Erba1
11Soumya Krishnapuram Sireesh ORCID1
11Stefano Ruzzu ORCID1

対象論文Papers

  1. JSSC
    2026
    A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication
    DOI
    Lucrezia Navarin, Karl Norling, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam, Andrea Neviani, Andrea Bevilacqua
    University of Padua · Infineon
  2. JSSC
    2026
    A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  3. JSSC
    2026
    An 80 MHz CT DSM With SMASH DAC Achieving 106.2 dB SFDR Without Linearity Calibration
    DOI
    Ahmed Abdelaal, John G. Kauffman, Matteo Dalla Longa, Francesco Conzatti, Maurits Ortmanns
    Universität Ulm · Infineon
  4. JSSC
    2025
    A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
    DOI
    Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
    Politecnico di Milano · Infineon
  5. JSSC
    2025
    A 4-bit RFDAC-Based FMCW Modulator for Automotive Radar
    DOI
    Soumya Krishnapuram Sireesh, Niels Christoffers, Sanaz Hadipour Abkenar, Christoph Wagner, Andreas Stelzer
    Infineon · Silicon Austria Labs (Austria) · Johannes Kepler University of Linz
  6. JSSC
    2025
    A 470- μ W, 102.6-dB DR, 20-kHz BW Calibration-Free ΔΣ Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC
    DOI
    Matteo Dalla Longa, Francesco Conzatti, Omar Ismail, Ahmed Abdelaal, John G. Kauffman, Maurits Ortmanns
    Infineon · Universität Ulm
  7. JSSC
    2025
    A 78.2-dB Dynamic Range Shunt-Based Current Sensor for BLDC Motor Control With 2.75- μ s Conversion Time and 0.4-mm² Active Area
    DOI
    Antonio Aprile, Jaya Satyanarayana Yarragunta, Andreas Fugger, Francesco Conzatti, Edoardo Bonizzoni, Piero Malcovati
    University of Pavia · Infineon
  8. JSSC
    2024
    A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
    DOI
    Francesco Tesolin, Simone M. Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  9. JSSC
    2024
    A 14–32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Gianluca Brozzetti, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti
    University of Pavia · Infineon
  10. JSSC
    2024
    A 22-dBA Digital Optical MEMS Microphone
    DOI
    Niccolò de Milleri, Luca Valli, Marc Fueldner, Andreas Wiesbauer, Andrea Baschirotto
    Infineon · University of Milano-Bicocca · Infineon
  11. JSSC
    2024
    Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
    DOI
    Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
    University of Padua · Infineon
  12. JSSC
    2023
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  13. JSSC
    2023
    A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop
    DOI
    Amirhossein Jouyaeian, Qinwen Fan, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa
    Delft University of Technology · Infineon
  14. JSSC
    2023
    A Hybrid Magnetic Current Sensor With a Multiplexed Ripple-Reduction Loop
    DOI
    Amirhossein Jouyaeian, Qinwen Fan, Roger Zamparette, Udo Ausserlechner, Mario Motz, Kofi A. A. Makinwa
    Delft University of Technology · Infineon
  15. JSSC
    2023
    A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  16. JSSC
    2022
    A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
    DOI
    Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
    University of Padua · Lund University · Infineon
  17. JSSC
    2022
    A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
    DOI
    Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Infineon
  18. JSSC
    2022
    A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
    DOI
    Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Qualcomm · Infineon · University College Dublin
  19. JSSC
    2022
    A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
    DOI
    Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
    University of Pavia · University of Padua · Infineon
  20. JSSC
    2022
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
    DOI
    Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · Qualcomm · University of Padua
  21. JSSC
    2022
    Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
    DOI
    Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
    Infineon · Politecnico di Milano
  22. JSSC
    2022
    Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance
    DOI
    Alessandro Franceschin, Domenico Riccardi, Andrea Mazzanti
    University of Pavia · STMicroelectronics · Infineon