企業・研究機関Company / Institute · スイスSwitzerland · 2022–2026 LIVE

Integrated Systems Laboratory

世界World 28位 (0 pt) · 対象論文Papers 10

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

JSSCCICCESSERC

数値表を表示Show table

会議・論文誌Venue	2022	2023	2024	2025	2026
JSSC	–	–	2	1	1
CICC	–	–	–	–	2
ESSERC	1	1	1	1	–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌Venue	フルFull	筆頭First	按分Frac.	順位Rank
ISSCC Tier 1	0	0	0.00	–
VLSI Tier 1	0	0	0.00	–
JSSC Tier 1	4	3	1.08	世界World #43
CICC Tier 2	2	1	0.75	世界World #13
A-SSCC Tier 2	0	0	0.00	–
ESSERC Tier 2	4	1	0.78	世界World #19

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

CICC
2026

A Low-Power 1.2 TFLOPS/W Merge-Split RVV Processor for Mixed Scalar-Vector Workloads
DOI
Mattia Sinigaglia, Marco Bertuletti, Gianmarco Ottavi, Amirhossein Kiamarzi, Matteo Perotti, Giuseppe Tagliavini, Luca Benini, Davide Rossi

University of Bologna · Integrated Systems Laboratory
CICC
2026

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
DOI
Paul Scheffler, Thomas Benz, Tim Fischer, Lorenzo Leone, Sina Arjmandpour, Luca Benini

ETH Zurich · Integrated Systems Laboratory
JSSC
2026

A 40k-Pixel Multimodal Biophysiology Monitoring Platform With 10k Concurrent Electrophysiology Channels and a Mixer-Embedded Σ Δ Impedance Sensor
DOI
Hangxing Liu, Fuze Jiang, Jingjing Zang, Marco Saif, Thomas Burger, Stephan C. F. Neuhauss, Hua Wang

ETH Zurich · Integrated Systems Laboratory · University of Zurich
ESSERC
2025

A 410 GFLOP/s, 64 RISC-V Cores, 204.8 GBps Shared-Memory Cluster in 12 nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN
DOI
Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, Luca Benini

ETH Zurich · Integrated Systems Laboratory
JSSC
2025

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET
DOI
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini

ETH Zurich · Integrated Systems Laboratory · University of Bologna · Stanford University
ESSERC
2024

A CMOS Molecular Sensor for Personalized Diagnostics Featuring Enzyme-Free Reading and Encoding of Viral Variants at Single-Nucleotide Resolution
DOI
Marco Saif, Fuze Jiang, Hangxing Liu, Adam Wang, Zhikai Huang, Yuguo Sheng, Dongwon Lee, Thomas Burger, Hua Wang

ETH Zurich · Integrated Systems Laboratory
JSSC
2024

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing
DOI
Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggiman, Hayate Okuhara, Luca Benini

University of Bologna · ETH Zurich · Integrated Systems Laboratory · National University of Singapore
JSSC
2024

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine
DOI
Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini

ETH Zurich · Integrated Systems Laboratory · University of Bologna · Universidad de Los Andes, Chile
ESSERC
2023

A 256-Channel In-Pixel Electrochemical Platform in CMOS for Rapid Isothermal Genetic Amplification and Screening
DOI
Hangxing Liu, Fuze Jiang, Dongwon Lee, Yuguo Sheng, Adam Wang, Marco Saif, Ying Kong, Zhikai Huang, Thomas Burger, Jing Wang, Hua Wang

ETH Zurich · Institute of Environmental Engineering · Integrated Systems Laboratory
ESSERC
2022

Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training
DOI
Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti

University of Bologna · Integrated Systems Laboratory