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大学University · 中国China · 2022–2026 LIVE

National University of Defense Technology

中国China 16位 (0 pt) · 世界World 25位 (0 pt) · 対象論文Papers 13

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

012345202220232024 CICC: 12024 A-SSCC: 22024 ESSERC: 2520242025 ISSCC: 12025 JSSC: 4520252026 JSSC: 12026 CICC: 232026
ISSCCJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC–––1–
JSSC–––41
CICC––1–2
A-SSCC––2––
ESSERC––2––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1110.64中国China #24 · 世界World #112
VLSI Tier 1000.00–
JSSC Tier 1521.48中国China #21 · 世界World #93
CICC Tier 2311.28中国China #19 · 世界World #65
A-SSCC Tier 2221.05中国China #19 · 世界World #53
ESSERC Tier 2211.20中国China #17 · 世界World #74

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A 157-Gb/s/mm 1.55-pJ/bit Correlated PAM4 Transceiver with Immunity to Crosstalk, Simultaneous Switching and Common-Mode Noise for High-Density Interconnect in 28nm CMOS
    DOI
    Geng Zhang, Fangxu Lv, Mingche Lai, Liquan Xiao, Ruixiao Kuai, Liangyong Yuan, Chao Fan, Lizhou Wu, Guohe Zhang
    National University of Defense Technology · Xi'an Jiaotong University
  2. CICC
    2026
    A 175-dB FoM S 12-bit 400-MS/s Pipeline-SAR ADC With an Optimized Detect-and-Skip Technique and a High-Efficiency Gain-Calibration-Free Amplification Scheme
    DOI
    Jiang Xu, Xuqiang Zheng, Zedong Wang, Hua Xu, Sai Li, Fangxu Lv, Mingche Lai, Xinyu Liu
    Chinese Academy of Sciences · National University of Defense Technology
  3. JSSC
    2026
    A Compact Low-Jitter All-Digital Fractional Output Divider Using Split-DTC-Based Background Calibration
    DOI
    Deng Luo, Yan Yu, Jianjun Chen, Yang Guo, Yaqing Chi, Guofang Yu, Hao Ding, Jing Xiao, Hao Gao, Ming Tao, Kai Tang, Bin Liang
    National University of Defense Technology · Hunan University · Southeast University
  4. ISSCC
    2025
    A 0.024mm2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration
    DOI
    Yan Yu, Deng Luo, Jianjun Chen, Yang Guo, Bin Liang, Yaqing Chi, Hanhan Sun, Jing Xiao, Hao Gao, Ming Tao, Kai Tang
    National University of Defense Technology · Hunan University · Southeast University
  5. JSSC
    2025
    A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS
    DOI
    Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
    Chinese Academy of Sciences · National University of Defense Technology
  6. JSSC
    2025
    A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment
    DOI
    Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu
    Chinese Academy of Sciences · National University of Defense Technology
  7. JSSC
    2025
    CRFF: A Static Contention-Free 23T Flip-Flop With Three Clock Load Transistors for Ultra-Low-Power Applications
    DOI
    Kun Su, Mingche Lai, Jieyu Li, Jingkun Duan, Shi Xu, Zhang Luo, Weifeng He
    Shanghai Jiao Tong University · National University of Defense Technology
  8. JSSC
    2025
    Design of a Compact Low-Power Sub-2.4-GHz Transceiver for Medical Band Applications
    DOI
    Heng Huang, Xiliang Liu, Zijian Tang, Wei Song, Yuan Ma, Yuwei Zhang, Xiaoyan Ma, Milin Zhang, Jintao Wang, Kai Lu, Zhihua Wang, Guolin Li
    National University of Defense Technology · Tsinghua University
  9. A-SSCC
    2024
    A Fully Integrated 400MHz Band Transceiver with a 96Mbps 16QAM Transmitter and a Phase Tracking Receiver in 40-nm CMOS
    DOI
    Heng Huang, Xiliang Liu, Zijian Tang, Wei Song, Yuan Ma, Ruixuan Pei, Yuwei Zhang, Xiaoyan Ma, Milin Zhang, Jintao Wang, Kai Lu, Zhihua Wang, Guolin Li
    National University of Defense Technology · Tsinghua University
  10. A-SSCC
    2024
    A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver
    DOI
    Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu
    National University of Defense Technology · Chinese Academy of Sciences
  11. CICC
    2024
    An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM
    DOI
    Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu
    Chinese Academy of Sciences · National University of Defense Technology
  12. ESSERC
    2024
    A 112Gb/s PAM4 Retimer Transceiver with Jitter-Filtering Clocking Scheme and BER Optimization Scoring 252fsrms Clock Jitter and 10-12 BER
    DOI
    Hua Xu, Xuqiang Zheng, Zedong Wang, Yu He, Fangxu Lv, Mingche Lai, Zunsong Yang, Xuan Guo, Zhi Jin, Xinyu Liu
    Chinese Academy of Sciences · National University of Defense Technology
  13. ESSERC
    2024
    A 61.4Gb/s/mm 1.42-pJ/b Symmetric Correlated Coding Wireline Transceiver With Single-Ended Crosstalk Cancelling for D2D Interconnection
    DOI
    Geng Zhang, Mingche Lai, Fangxu Lv, Liquan Xiao, Weixia Xu, Liangyong Yuan, Ruixiao Kuai, Heng Huang, Kewei Xin
    National University of Defense Technology