VLSI · 2022–2026 LIVE

NVIDIA

対象論文Papers 10 · 筆頭著者first author 10 · 著者按分fractional 10.00 · アメリカUSA #3 · 世界World #8

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Brian Zimmer ORCID	7
1	C. Thomas Gray ORCID	7
3	Stephen G. Tell	6
4	Nikola Nedovic	5
4	Sanquan Song ORCID	5
6	Xi Chen	4
6	Yoshinori Nishi ORCID	4
8	John W. Poulton ORCID	3
8	William J. Dally ORCID	3
10	Angad Rekhi	2
10	Benjamin G. Lee ORCID	2
10	Brucek Khailany ORCID	2
10	Georgios Kalogerakis	2
10	John M. Wilson ORCID	2
10	Li Xu ORCID	2
10	Nandish Mehta ORCID	2
10	Walker J. Turner ORCID	2
10	Ward Lopes	2
19	Ben Keller ORCID	1
19	Chenhui Deng	1
19	Chia-Tung Ho	1
19	Christos Kozyrakis	1
19	Haoxing Ren	1
19	Jason Clemons	1
19	Jing Gong	1
19	John Y. Chen	1
19	Qijing Huang	1
19	Rangharajan Venkatesan	1
19	Steve Dai ORCID	1
19	Steve Tell	1
19	Sudhir S. Kudva	1
19	Thomas H. Greer	1
19	Trey Greer	1
19	Wenqi Jiang	1
19	Yunsheng Bai	1

対象論文Papers

VLSI
2026

A $\mathbf{3 2 G b} / \mathbf{s}$ Optical Receiver Utilizing a Differential TIA with $- 1 7. 3 d B m$ Sensitivity in a 3D-Stacked Silicon Photonics Platform
DOI
Georgios Kalogerakis, Sanquan Song, Li Xu, Nandish Mehta, Angad Rekhi, Nikola Nedovic, Benjamin G. Lee, Brian Zimmer, Steve Tell, Yoshinori Nishi, Xi Chen, Ward Lopes, Trey Greer, C. Thomas Gray

NVIDIA
VLSI
2026

A 0.416-pJ/b, 32-Gb/s 3D-Stacked Optical NRZ Receiver with −18.5-dBm OMA Sensitivity Using Self-Timed Decision Feedback Equalization
DOI
Li Xu, Sanquan Song, Nikola Nedovic, Georgios Kalogerakis, Nandish Mehta, Angad Rekhi, Brian Zimmer, Stephen G. Tell, Yoshinori Nishi, Xi Chen, Ward Lopes, Benjamin G. Lee, Thomas H. Greer, John W. Poulton, C. Thomas Gray

NVIDIA
VLSI
2026

Enabling the Robotic Revolution: Bridging Performance Gap Between Present and Future
DOI
Qijing Huang, Wenqi Jiang, Christos Kozyrakis, Jason Clemons

NVIDIA
VLSI
2025

A 77 fJ/Bit 8 Gbps Low-Latency Self-Timed Die-to-Die Link for 2.5D and 3D Interconnect in 3nm
DOI
Brian Zimmer, Stephen G. Tell, C. Thomas Gray

NVIDIA
VLSI
2025

Innovate VLSI for AI Growth
DOI
John Y. Chen

NVIDIA
VLSI
2025

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
DOI
Chia-Tung Ho, Jing Gong, Yunsheng Bai, Chenhui Deng, Haoxing Ren, Brucek Khailany

NVIDIA
VLSI
2023

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
DOI
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

NVIDIA
VLSI
2022

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
DOI
Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray

NVIDIA
VLSI
2022

A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm
DOI
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany

NVIDIA
VLSI
2022

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process
DOI
Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray

NVIDIA