CICC · 2022–2026 LIVE

Politecnico di Milano

対象論文Papers 7 · 筆頭著者first author 7 · 著者按分fractional 6.62 · 世界World #30

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Salvatore Levantino ORCID	7
2	Andrea L. Lacaita ORCID	6
3	Simone M. Dartizio ORCID	5
4	Michele Rossoni ORCID	4
5	Carlo Samori ORCID	3
5	Francesco Tesolin ORCID	3
5	Pietro Salvi ORCID	3
8	Damiano Fagotti ORCID	2
8	Daniele Lodi Rizzini ORCID	2
8	Giacomo Castoro ORCID	2
8	Luca Bertulessi ORCID	2
8	Riccardo Moleri ORCID	2
8	Stefano Gallucci ORCID	2
14	Alessia Ceroni ORCID	1
14	Alessio Santiccioli ORCID	1
14	Andrea Bonfanti ORCID	1
14	Francesco Buccoleri ORCID	1
14	Franceso Tesolin	1
14	Gabriele Bè ORCID	1
14	Gabriele Zanoletti ORCID	1
14	Luca Ricci ORCID	1
14	Michele Rocco ORCID	1

対象論文Papers

CICC
2026

A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mV pp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning
DOI
Stefano Gallucci, Daniele Lodi Rizzini, Riccardo Moleri, Michele Rossoni, Pietro Salvi, Damiano Fagotti, Franceso Tesolin, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

Politecnico di Milano
CICC
2026

A DTC-Based Digital PLL Achieving –64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC
DOI
Riccardo Moleri, Daniele Lodi Rizzini, Michele Rossoni, Damiano Fagotti, Pietro Salvi, Stefano Gallucci, Andrea Leonardo Lacaita, Salvatore Levantino, Simone Mattia Dartizio

Politecnico di Milano
CICC
2025

A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA
DOI
Gabriele Zanoletti, Gabriele Bè, Michele Rocco, Luca Ricci, Alessia Ceroni, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Andrea Bonfanti, Carlo Samori

Politecnico di Milano
CICC
2024

A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector
DOI
Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Politecnico di Milano
CICC
2024

A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC
DOI
Pietro Salvi, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino

Politecnico di Milano
CICC
2022

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
DOI
Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Politecnico di Milano · Infineon · University of Padua
CICC
2022

Recent Advances in High-Performance Frequency Synthesizer Design
DOI
Salvatore Levantino

Politecnico di Milano