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大学University · イタリアItaly · 2022–2026 LIVE

Politecnico di Milano

世界World 25位 (0 pt) · 対象論文Papers 44

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0246810122022 ISSCC: 12022 JSSC: 52022 CICC: 22022 ESSERC: 1920222023 ISSCC: 22023 VLSI: 12023 JSSC: 42023 ESSERC: 1820232024 ISSCC: 22024 VLSI: 12024 JSSC: 12024 CICC: 22024 ESSERC: 1720242025 ISSCC: 22025 VLSI: 22025 JSSC: 42025 CICC: 1920252026 ISSCC: 32026 VLSI: 12026 JSSC: 52026 CICC: 2112026
ISSCCVLSIJSSCCICCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC12223
VLSI–1121
JSSC54145
CICC2–212
ESSERC111––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 110109.12世界World #35
VLSI Tier 1554.60世界World #38
JSSC Tier 1191715.71世界World #36
CICC Tier 2776.62世界World #30
A-SSCC Tier 2000.00–
ESSERC Tier 2321.12世界World #53

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mV pp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning
    DOI
    Stefano Gallucci, Daniele Lodi Rizzini, Riccardo Moleri, Michele Rossoni, Pietro Salvi, Damiano Fagotti, Franceso Tesolin, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  2. CICC
    2026
    A DTC-Based Digital PLL Achieving –64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC
    DOI
    Riccardo Moleri, Daniele Lodi Rizzini, Michele Rossoni, Damiano Fagotti, Pietro Salvi, Stefano Gallucci, Andrea Leonardo Lacaita, Salvatore Levantino, Simone Mattia Dartizio
    Politecnico di Milano
  3. ISSCC
    2026
    11.3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension
    DOI
    Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Carlo Samori, Andrea Giovanni Bonfanti
    Politecnico di Milano
  4. ISSCC
    2026
    A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving −62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mV rms DTC Supply Noise
    DOI
    Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco Trotta, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  5. ISSCC
    2026
    A −66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC
    DOI
    Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  6. JSSC
    2026
    A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension
    DOI
    Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Be, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti
    Politecnico di Milano
  7. JSSC
    2026
    A Low Jitter Fractional- N Digital PLL Using a Supply-Insensitive Variable-Slope DTC
    DOI
    Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni R. Trotta, Andrea L. Lacaita, Simone M. Dartizio, Salvatore Levantino
    Politecnico di Milano
  8. JSSC
    2026
    A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique
    DOI
    Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  9. JSSC
    2026
    A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  10. JSSC
    2026
    A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS
    DOI
    Daniele Lodi Rizzini, Francesco Tesolin, Michele Rossoni, Riccardo Moleri, Filippo Osio, Andrea Mazzanti, Andrea L. Lacaita, Simone M. Dartizio, Salvatore Levantino
    Politecnico di Milano · University of Pavia
  11. VLSI
    2026
    A 0.5W/mm 2 -Power-Density, 91.6%-Peak-Efficiency, Resonant Dual-Path Interleaved DC-DC Converter
    DOI
    S. Zaffin, M. Leoncini, A. Bertolini, A. Dago, A. Gasparini, S. Levantino, M. Ghioni
    Politecnico di Milano · STMicroelectronics
  12. CICC
    2025
    A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA
    DOI
    Gabriele Zanoletti, Gabriele Bè, Michele Rocco, Luca Ricci, Alessia Ceroni, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Andrea Bonfanti, Carlo Samori
    Politecnico di Milano
  13. ISSCC
    2025
    34.2 A 380μW and −242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS
    DOI
    Simone Mattia Dartizio, Giacomo Castoro, Stefano Gallucci, Michele Rossoni, Riccardo Moleri, Francesco Tesolin, Pietro Salvi, Saleh Karman, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  14. ISSCC
    2025
    34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning
    DOI
    Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Simone Mattia Dartizio, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano
  15. JSSC
    2025
    A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
    DOI
    Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
    Politecnico di Milano · Infineon
  16. JSSC
    2025
    A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
    DOI
    Michele Rossoni, Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano
  17. JSSC
    2025
    A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators
    DOI
    Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Carlo Samori, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  18. JSSC
    2025
    A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
    DOI
    Pietro Salvi, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano
  19. VLSI
    2025
    A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC
    DOI
    D. Fagotti, S. M. Dartizio, F. Tesolin, R. Moleri, G. R. Trotta, M. Rossoni, S. Gallucci, P. Salvi, G. Castoro, D. Lodi Rizzini, A. L. Lacaita, S. Levantino
    Politecnico di Milano
  20. VLSI
    2025
    A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under $3 \text{mV}_{\text{pp}}$ Supply Ripple
    DOI
    M. Rossoni, R. Moleri, D. Lodi Rizzini, P. Salvi, S. Gallucci, G. Castoro, F. Tesolin, A. L. Lacaita, S. M. Dartizio, S. Levantino
    Politecnico di Milano
  21. CICC
    2024
    A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector
    DOI
    Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano
  22. CICC
    2024
    A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC
    DOI
    Pietro Salvi, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano
  23. ESSERC
    2024
    Robust and Compact Quaternary Symbol Coding 3Cells/2Bits16MB Embedded PCM Solution in 28nm FD-SOI CMOS with Automotive Grade
    DOI
    M. Carissimi, A. Tomasoni, A. Ventre, R. Grasso, M. Perroni, D. Manfrè, C. Torti, A. Molgora, A. Maurelli, A. Gandolfo, A. Cathelin, A. Bonfanti, F. Disegni
    STMicroelectronics · Politecnico di Milano
  24. ISSCC
    2024
    10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
    DOI
    Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell’Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano
  25. ISSCC
    2024
    10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
    DOI
    Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  26. JSSC
    2024
    A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
    DOI
    Francesco Tesolin, Simone M. Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  27. VLSI
    2024
    A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
    DOI
    Riccardo Moleri, Simone Mattia Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  28. ESSERC
    2023
    A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications
    DOI
    Paolo Melillo, Mauro Leoncini, Simone Zaffin, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
    Politecnico di Milano · STMicroelectronics
  29. ISSCC
    2023
    4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  30. ISSCC
    2023
    4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  31. JSSC
    2023
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  32. JSSC
    2023
    A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  33. JSSC
    2023
    A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
    DOI
    Francesco Tesolin, Simone M. Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Qualcomm
  34. JSSC
    2023
    Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power Quantum Entanglement Detection
    DOI
    Fabio Severini, Iris Cusini, Francesca Madonini, Davide Brescia, Robin Camphausen, Álvaro Cuevas, Simone Tisa, Federica Villa
    Politecnico di Milano · Institute of Photonic Sciences · Micro Photon Devices
  35. VLSI
    2023
    A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS
    DOI
    Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, Luca Bertulessi, Salvatore Levantino, Andrea Lacaita, Carlo Samori, Andrea Bonfanti
    Politecnico di Milano
  36. CICC
    2022
    A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  37. CICC
    2022
    Recent Advances in High-Performance Frequency Synthesizer Design
    DOI
    Salvatore Levantino
    Politecnico di Milano
  38. ESSERC
    2022
    Thermal switching of $\text{TiO}_{2}$ -based RRAM for parameter extraction and neuromorphic engineering
    DOI
    Alessandro Milozzi, Daniel Reiser, Andreas Drost, Thomas Neuner, Marc Tornow, Daniele Ielmini
    Politecnico di Milano · Fraunhofer Research Institution for Microsystems and Solid State Technologies · Technical University of Munich
  39. ISSCC
    2022
    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
    DOI
    Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  40. JSSC
    2022
    A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
    DOI
    Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Infineon
  41. JSSC
    2022
    A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
    DOI
    Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Qualcomm · Infineon · University College Dublin
  42. JSSC
    2022
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
    DOI
    Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · Qualcomm · University of Padua
  43. JSSC
    2022
    Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
    DOI
    Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
    Infineon · Politecnico di Milano
  44. JSSC
    2022
    Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC)
    DOI
    Rabia Tugce Yazicigil, Salvatore Levantino
    Boston University · Politecnico di Milano