TopSSCS
← Politecnico di Milano

ISSCC · 2022–2026 LIVE

Politecnico di Milano

対象論文Papers 10 · 筆頭著者first author 10 · 著者按分fractional 9.12 · 世界World #35

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Andrea L. Lacaita ORCID10
1Salvatore Levantino ORCID10
3Simone M. Dartizio ORCID9
4Michele Rossoni ORCID8
5Carlo Samori ORCID7
5Francesco Tesolin ORCID7
7Francesco Buccoleri ORCID5
7Giacomo Castoro ORCID5
9Luca Bertulessi ORCID4
9Pietro Salvi ORCID4
9Riccardo Moleri ORCID4
9Stefano Gallucci ORCID4
13Daniele Lodi Rizzini ORCID3
14Damiano Fagotti ORCID2
15Alessia Ceroni ORCID1
15Alessio Santiccioli ORCID1
15Andrea Giovanni Bonfanti1
15Gabriele Bè ORCID1
15Gabriele Zanoletti ORCID1
15Giacomo Tombolan ORCID1
15Giovanni Rocco Trotta1
15Luca Lanzoni1
15Luca Ricci ORCID1
15Michele Rocco ORCID1
15Riccardo Dell’Orto ORCID1

対象論文Papers

  1. ISSCC
    2026
    11.3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension
    DOI
    Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Carlo Samori, Andrea Giovanni Bonfanti
    Politecnico di Milano
  2. ISSCC
    2026
    A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving −62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mV rms DTC Supply Noise
    DOI
    Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco Trotta, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  3. ISSCC
    2026
    A −66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC
    DOI
    Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  4. ISSCC
    2025
    34.2 A 380μW and −242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS
    DOI
    Simone Mattia Dartizio, Giacomo Castoro, Stefano Gallucci, Michele Rossoni, Riccardo Moleri, Francesco Tesolin, Pietro Salvi, Saleh Karman, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  5. ISSCC
    2025
    34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning
    DOI
    Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Simone Mattia Dartizio, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano
  6. ISSCC
    2024
    10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
    DOI
    Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell’Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano
  7. ISSCC
    2024
    10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
    DOI
    Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  8. ISSCC
    2023
    4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  9. ISSCC
    2023
    4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  10. ISSCC
    2022
    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
    DOI
    Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua