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JSSC · 2022–2026 LIVE

Politecnico di Milano

対象論文Papers 19 · 筆頭著者first author 17 · 著者按分fractional 15.71 · 世界World #36

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Salvatore Levantino ORCID18
2Andrea L. Lacaita ORCID17
3Simone M. Dartizio ORCID13
4Carlo Samori ORCID12
4Francesco Tesolin ORCID12
6Michele Rossoni ORCID9
7Francesco Buccoleri ORCID8
8Giacomo Castoro ORCID7
8Luca Bertulessi ORCID7
10Alessio Santiccioli ORCID5
11Riccardo Moleri ORCID4
12Daniele Lodi Rizzini ORCID3
12Pietro Salvi ORCID3
14Andrea Bonfanti ORCID2
14Angelo Parisi ORCID2
14Gabriele Bè ORCID2
14Gabriele Zanoletti ORCID2
14Luca Ricci ORCID2
14Mario Mercandelli ORCID2
14Michele Rocco ORCID2
14Stefano Gallucci ORCID2
22Abanob Shehata ORCID1
22Alessia Ceroni ORCID1
22Damiano Fagotti ORCID1
22Davide Brescia1
22Fabio Severini ORCID1
22Federica Villa ORCID1
22Filippo Osio ORCID1
22Francesca Madonini ORCID1
22Giacomo Tombolan ORCID1
22Giovanni R. Trotta ORCID1
22Iris Cusini ORCID1
22Riccardo Dell’Orto ORCID1
22Saleh Karman ORCID1

対象論文Papers

  1. JSSC
    2026
    A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension
    DOI
    Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Be, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti
    Politecnico di Milano
  2. JSSC
    2026
    A Low Jitter Fractional- N Digital PLL Using a Supply-Insensitive Variable-Slope DTC
    DOI
    Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni R. Trotta, Andrea L. Lacaita, Simone M. Dartizio, Salvatore Levantino
    Politecnico di Milano
  3. JSSC
    2026
    A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique
    DOI
    Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  4. JSSC
    2026
    A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
    DOI
    Giacomo Castoro, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  5. JSSC
    2026
    A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS
    DOI
    Daniele Lodi Rizzini, Francesco Tesolin, Michele Rossoni, Riccardo Moleri, Filippo Osio, Andrea Mazzanti, Andrea L. Lacaita, Simone M. Dartizio, Salvatore Levantino
    Politecnico di Milano · University of Pavia
  6. JSSC
    2025
    A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
    DOI
    Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
    Politecnico di Milano · Infineon
  7. JSSC
    2025
    A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
    DOI
    Michele Rossoni, Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano
  8. JSSC
    2025
    A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators
    DOI
    Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Carlo Samori, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
    Politecnico di Milano
  9. JSSC
    2025
    A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
    DOI
    Pietro Salvi, Simone M. Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano
  10. JSSC
    2024
    A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
    DOI
    Francesco Tesolin, Simone M. Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  11. JSSC
    2023
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  12. JSSC
    2023
    A Low-Spur and Low-Jitter Fractional- N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
    DOI
    Simone M. Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon
  13. JSSC
    2023
    A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
    DOI
    Francesco Tesolin, Simone M. Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Qualcomm
  14. JSSC
    2023
    Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power Quantum Entanglement Detection
    DOI
    Fabio Severini, Iris Cusini, Francesca Madonini, Davide Brescia, Robin Camphausen, Álvaro Cuevas, Simone Tisa, Federica Villa
    Politecnico di Milano · Institute of Photonic Sciences · Micro Photon Devices
  15. JSSC
    2022
    A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
    DOI
    Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Infineon
  16. JSSC
    2022
    A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
    DOI
    Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Qualcomm · Infineon · University College Dublin
  17. JSSC
    2022
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
    DOI
    Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · Qualcomm · University of Padua
  18. JSSC
    2022
    Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
    DOI
    Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
    Infineon · Politecnico di Milano
  19. JSSC
    2022
    Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC)
    DOI
    Rabia Tugce Yazicigil, Salvatore Levantino
    Boston University · Politecnico di Milano