企業・研究機関Company / Institute · 韓国Korea · 2022–2026 LIVE

Samsung

韓国Korea 1位 (112.5 pt) · 世界World 1位 (104 pt) · 対象論文Papers 317

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

ISSCCVLSIJSSCCICCA-SSCCESSERC

数値表を表示Show table

会議・論文誌Venue	2022	2023	2024	2025	2026
ISSCC	22	10	19	17	16
VLSI	19	12	13	11	13
JSSC	17	22	19	18	20
CICC	5	2	2	3	2
A-SSCC	13	10	12	8	–
ESSERC	3	1	3	5	–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌Venue	フルFull	筆頭First	按分Frac.	順位Rank
ISSCC Tier 1	84	68	67.58	韓国Korea #1 · 世界World #1
VLSI Tier 1	68	40	46.80	韓国Korea #1 · 世界World #1
JSSC Tier 1	96	41	46.60	韓国Korea #1 · 世界World #1
CICC Tier 2	14	6	6.61	韓国Korea #1 · 世界World #2
A-SSCC Tier 2	43	24	22.62	韓国Korea #1 · 世界World #1
ESSERC Tier 2	12	3	3.73	韓国Korea #1 · 世界World #3

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

CICC
2026

A 97.1%-Efficient Single-Mode Fine-Multilevel Buck-Boost (SMFL-BB) Converter Achieving Sub-8mV Ripple with a 1mm 3 -Volume Inductor for Flicker-Free Mobile OLED Displays
DOI
Sueon Park, Jun-Gi Lee, Jae-Hyun Kim, Dong-Kyu Kim, Sung-Chun Park, Yongjae Lee, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
CICC
2026

A Simultaneous 16-Channel Adiabatic Charge-Tracking Stimulator with 87.4% Stimulator Efficiency and Low Load Sensitivity
DOI
Eojin Kim, Janghwan Kim, Jaeseong Park, Seongjae Moon, Geunchang Seong, Su Yeon Jeon, Seonae Jang, Young Sang Cho, Sohmyung Ha, Chul Kim

Korea Advanced Institute of Science and Technology · Samsung · Sungkyunkwan University · New York University Abu Dhabi
ISSCC
2026

15.10 A Vertical-Cell-Transistor-Based 4F 2 DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding
DOI
Hyunchul Yoon, Youngseok Park, Tae Jin Park, Suk Lae Kim, Seungjae Jung, Daesun Kim, Kyunghwan Kim, Yongjun Kim, KyuChang Kang, Bokyeon Won, Sang-Hoon Jung, Seunghan Woo, Donggeon Kim, Jonghyuk Kim, In Jung, Junsoo Kim, Jae-Joon Song, InCheol Nam, Young-Hun Seo, Sungsoo Yim, Jemin Park, Changsik Yoo, SangJoon Hwang

Samsung
ISSCC
2026

15.3 An 8nm eMRAM for Auto-G1 with a 125MHz Read Speed at 0.6V and 19.94Mb/mm 2 Density
DOI
Hyunjin Shin, Gyuseong Kang, Yeseul Kim, Dohui Kim, Kyuseong Kim, Sunkyu Lee, Hangil Lee, Sanggyeong Won, Mijoung Kim, Jaeho Lee, Seungpil Ko, Jaechul Shim, Shinhee Han, Kiseok Suh, Sohee Hwang, Hyunchang Lee, Jonghoon Jung, Sanghoon Baek

Samsung
ISSCC
2026

15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST
DOI
Sunghwan Joo, Jinyeon Kim, Yongsun Lee, Ji-Young Kim, Youngsik Lee, Yong-Min Kim, ChiSung Oh, Kyu-Ha Shim, Haesuk Lee, Young-Yong Byun, ChangHyun Bae, Joohwan Kim, Je-Min Ryu, Shin-haeng Kang, Jaehoon Lee, Young-Uk Chang, JaeKyung Lee, JongTae Hwang, Daehwan Seo, Ki-Heon Na, Young Guen Song, Daihyun Lim, Kyung-Soo Ha, Young-Soo Sohn, Sang-Joon Hwang

Samsung
ISSCC
2026

16.9 A 96.6% Single-Mode Hybrid Dual-Path Buck-Boost Converter with Conduction Loss Reduction through Conversion-Ratio-Based Adaptive 3-Phase Control
DOI
Minsu Kim, Yunho Lee, Hyunjun Park, Hongseok Kim, Woojoong Jung, Minwoo Kim, Junhyun Bae, Hyoung-Seok Oh, Hwayeal Yu, Hyung-Min Lee

Korea University · Samsung
ISSCC
2026

24.1 A 28nm CMOS 1-Chip In-Pixel Memory Backplane Circuit with Pixel-Level Sensing and Compensation for 6652-PPI MicroLED AR Glasses
DOI
Yongil Kwon, Sunkwon Kim, Youngkil Choi, Taehyun Kwon, Seongyoung Ryu, Sewhan Na, Kangjoo Kim, Uijong Song, Hyun-Wook Lim, Jongwoo Lee, Jae-Yeol Lee

Samsung
ISSCC
2026

24.6 A Touch-Embedded OLED Display-Driver IC with Display Noise Referencing and Display Coupling Noise Prediction Based on Dedicated Neural Networks for Mobile Applications with CoE Display
DOI
Yun-Rae Jo, Sewhan Na, Sanho Byun, Junchul Park, Gyeongmin Ha, Jiheon Ok, Tae-Gyun Song, Woo-Nyoung Lee, Jihyun Lee, Hyun-Wook Lim, Siwoo Kim, Jae-Youl Lee

Samsung
ISSCC
2026

34.2 Compact, Low-Power 60-and-77GHz 4T/4R Multi-Mode FMCW Radar RFICs in 28nm CMOS
DOI
Byeong-Taek Moon, Mingyuan Li, Junseuk Suh, Minseob Lee, Doyoon Kim, Kyunghwan Kim, Geonho Park, Goeun Baek, Byungho Yook, Dooseok Choi, Kyungwoo Yoo, Junseong Kim, Taewoo Yu, Seonghyeon Kang, Hyeonsu Jo, Juhee Son, Sangsung Lee, Pak-Kim Lau, Siuchuang Ivan Lu, Gregory Eric Rogers, Ajaypat Jain, Jian Wang, Viduneth Ariyarathna, Wan Jong Kim, Oren Eliezer, Gennady Feygin, Wen Zhou, Kyoung-Jun Moon, Jaehyun Chung, Woncheol Lee, Seongjung Kim, Jonghyun Kim, Joonggeun Lee, Taeyeon Kim, Sungjoo Kim, Youngki Lee, Yonghwan Harold Jang, Sai Krishna Rayudu, Shihchieh Chien, Ying Chen, Hyungsun Lim, Kidong Kang, Sungjun Lee, Joonhee Lee, Jeongyeol Bae, Hyun-Gi Seok, Pranav Dayal, Wanghua Wu, Hyun-Chul Park, Joonhoi Hur, Sangmin Yoo, Chan-Hong Park, Joonsuk Kim

Samsung
ISSCC
2026

37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE
DOI
Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang, Kyoungwon Lee, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew

Samsung
ISSCC
2026

37.7 A 12.8Gb/s Parallel Receiver with a One-Way Self-Training Scheme for Equalizing ISI and Reflections in Multi-Drop Memory Interfaces
DOI
Ji-Won Moon, Taehyeon Kim, Minwook Kim, Hyeonwoo Seong, Jewon Lee, Jeongbin Park, Dongjun Park, Jaehoon Lee, Jung-June Park, Chiweon Yoon, Jae-Yoon Sim, Seon-Kyoo Lee

Pohang University of Science and Technology · Samsung
ISSCC
2026

A 0.6V 625um 2 Fully Stacked RC-Based Temperature Sensor Using Low TCR Metal Resistor Achieving 0.017nJ.% 2 -Accuracy FoM in 2nm Gate-All-Around Process
DOI
Haejung Choi, Jooseong Kim, Woojoong Jung, Sungmin Yoo, Jun-Hyeok Yang, Sunghyuck Lee, Jihye Park, Michael Choi, Ben Rhew

Samsung
ISSCC
2026

A 0.87pJ/b 17Gb/s/pin Parallel Receiver with a Local DQS Recovery for a Supply-Noise-Tolerant DQS Distribution in High-Performance NAND Flash Interfaces
DOI
Byeong-Chan Kim, Kyongsu Lee, Dongjun Park, Jung-June Park, Chiweon Yoon, Jae-Yoon Sim, Seon-Kyoo Lee

Pohang University of Science and Technology · Samsung
ISSCC
2026

A 1.09e − -Random-Noise 1.5μm-Pixel-Pitch 12MP Global-Shutter-Equivalent CMOS Image Sensor with 3μm Digital Pixels Using Quad-Phase-Staggered Zigzag Readout and Motion Compensation
DOI
Sanggwon Lee, Sun-Young Yoo, Yeongseok Shim, Yong-Suk Choi, Daehee Bae, Masamichi Ito, Deokha Shin, Si-Gyoung Koo, Sung-Jae Byun, Gihwan Cho, Hyukbin Kwon, Jaehun Jeong, Bumjun Kim, Su-Hyun Han, Youna Lee, Hiroyuki Sugihara, Junghoon Jung, Suksan Kim, Kyungtae Lim, Wonoh Ryu, Yongjun Kim, Seung-Sik Kim, Heesung Shim, Min-Woong Seo, Jae-kyu Lee, Jonghyun Go, Jaihyuk Song

Samsung
ISSCC
2026

A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme
DOI
Kiheung Kim, Hong-Joo Song, Youngdo Um, Jinhun Jang, Seungjun Lee, Hoseok Seol, Hye-Jung Kwon, Ji-Hwan Seol, Hoon Shin, Jaehyung Lee, JongMoon Choi, Sung-Woo Yoon, Sang Yun Kim, Dongkeon Lee, Minsoo Jang, Daehyun Kwon, Sangyong Lee, Jinguk Kim, Jonghyuk Kim, In Jung, Taeha Song, Chang Won Kim, Seung Ho Baek, Jinyong Choi, Young-Hun Seo, Won Ho Choi, Changsik Yoo, SangJoon Hwang

Samsung
ISSCC
2026

A 77GHz 8-bit CMOS Phase Shifter Adopting a Nested-Vector-Based Error Correction with 0.33°/0.07dB RMS-Error for MIMO Radar Applications
DOI
Geonho Park, Byeong-Taek Moon, Kyunghwan Kim, Doyoon Kim, Goeun Baek, Byungho Yook, Hyun-Chul Park, Chan-Hong Park

Samsung
ISSCC
2026

A High Back-Off Efficiency Unequal-Stacked Doherty Power Amplifier Achieving 16.7dBm P avg in a 22nm FDSOI CMOS Technology for 5G FR2 Applications
DOI
Seungwon Park, Jooseok Lee, Seungjae Baek, Taewan Kim, Yifei Chen, Sehyug Jeon, Sung-gi Yang

Samsung
ISSCC
2026

A PVT Variation- and Attack-Tolerant Metastability-Based TRNG Using Binary Search in 2nm
DOI
Yelim Youn, Yong Lim, Jongmi Lee, Dongyeon Hong, Wan Kim, Yong-Sik Kwak, Kyoung-Jun Moon, Bogyeong Kang, Sangmin Yoo

Samsung
JSSC
2026

A 0.2-mW 250-kHz-BW Fully Dynamic kT/C Noise-Shaping Discrete-Time Delta-Sigma Modulator With SAR-Assisted Input Feedforward and Digital Noise Coupling
DOI
Young-Hun Moon, Kun-Woo Park, Krishnakanth R, Kyunghoon Kim, Minho Kwon, Min-Jae Seo, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung · University of Seoul
JSSC
2026

A 1.16 e-rms Temporal Random Noise, 123-dB High Dynamic Range, 2.988- μ m Pitch 3-Mpixel Three-Stacked Digital Pixel Sensor for Versatile Applications
DOI
Min-Woong Seo, Yong-Suk Choi, Sanggwon Lee, Yeongseok Shim, Gihwan Cho, Daehee Bae, Masamichi Ito, Jaehun Jeong, Hiroyuki Sugihara, Si-Gyoung Koo, Sung-Jae Byun, Hyukbin Kwon, Youna Lee, Bumjun Kim, Su-Hyun Han, Suksan Kim, Wonoh Ryu, Kwan-Sik Kim, Yongjun Kim, Seung-Sik Kim, Junghoon Jung, Sun-Young Yoo, Jinkyeong Heo, Seung-Chul Shin, Heesung Shim, Jae-Kyu Lee, Jonghyun Go, Jaihyuk Song

Samsung
JSSC
2026

A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration
DOI
Chang-Un Park, Jae-Hyun Chung, Chunsuk Kim, Hyun-Woo Shin, Charlie Tahar, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2026

A 136.6-dB-DR 174.3-dB-FoM S Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop
DOI
Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Yeonjae Shin, Jeongyoon Wie, Seungyeob Baik, Hongki Kang, Minyoung Song, Jong-Hyeok Yoon, Junghyup Lee

Georgia Institute of Technology · Samsung · Daegu Gyeongbuk Institute of Science and Technology · Korea Institute of Nuclear Safety · Seoul National University
JSSC
2026

A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead
DOI
Jungmyung Kang, Keonhee Cho, Sekeon Kim, Giseok Kim, Hyunjun Kim, Dongwook Seo, Sangyeop Baeck, Sei Seung Yoon, Seong-Ook Jung

Samsung · Yonsei University
JSSC
2026

A 2-nm All-Digital LPDDR6 PHY With Quarter-Rate Clocking and Multi-Level FIFO-Based Speculative DFE
DOI
Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Hyo-Gyuem Rhew, Kwanyeob Chae

Samsung
JSSC
2026

A 28-nm CMOS 1-Chip In-Pixel Memory Backplane Circuit for 1800 × 1350 6652-PPI MicroLED AR Glasses With Per-Pixel Current Sensing and Compensation
DOI
Sunkwon Kim, Yongil Kwon, Youngkil Choi, Taehyun Kwon, Seongyoung Ryu, Sewhan Na, Kangjoo Kim, Uijong Song, Heejin Lee, Hyun-Wook Lim, Jongwoo Lee, Jae-Youl Lee

Samsung
JSSC
2026

A 77-GHz 8-bit Vector-Sum Phase Shifter With a Nested-Vector-Based Error Correction Scheme for MIMO Radars
DOI
Geonho Park, Byeong-Taek Moon, Kyunghwan Kim, Doyoon Kim, Goeun Baek, Byungho Yook, Hyun-Chul Park, Chan-Hong Park

Samsung
JSSC
2026

A Fast-Settling mm-Wave LO With I/Q-Calibrated SSB Mixer and Frequency-Tuned ILO Filter Achieving Sub-ns Settling Time and −56 dBc Spur
DOI
Jaewon Oh, Cheol So, Hyojun Kim, Songcheol Hong, SeongHwan Cho

Samsung · Samsung · University of California, Santa Barbara · Korea Aerospace Research Institute · Korea Advanced Institute of Science and Technology
JSSC
2026

A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application
DOI
Sekeon Kim, Giseok Kim, Kyeongrim Baek, Keonhee Cho, Hyunjun Kim, Yeonho Jung, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung

Yonsei University · Samsung
JSSC
2026

A Hybrid Touch Sensing AFE With Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load
DOI
Seung Hun Choi, Jun Yeol An, Jaewoong Ahn, Si-Woo Kim, Jae-Youl Lee, Yoon-Kyung Choi, Hyung-Min Lee

Korea University · Samsung
JSSC
2026

A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues
DOI
Jae-Geun Lim, Jun-Ho Boo, Jae-Hyuk Lee, Hyoung-Jung Kim, Byeongho Yu, Kang-Il Cho, Sungho Lee, Un-Ku Moon, Gil-Cho Ahn

Sogang University · Hankuk University of Foreign Studies · Samsung · Korea Electronics Technology Institute · Oregon State University
JSSC
2026

A Low-Jitter Fractional- N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique
DOI
Yuhwan Shin, Juyeop Kim, Junseok Lee, Yongwoo Jo, Jaehyouk Choi

Korea Advanced Institute of Science and Technology · Samsung · Samsung · Seoul National University
JSSC
2026

A Real-Time Link-Adaptive 3-D Resonant Current-Mode Wireless Receiver With Self-Optimizing Control
DOI
Jong-Hun Kim, Seung-Ju Lee, Seogyong Jeong, Yeon-Woo Jeong, Mun-Jung Cho, Hyuntak Jeon, Se-Un Shin

Pohang University of Science and Technology · Samsung · Chungbuk National University
JSSC
2026

A Scalable 1024-Channel VCO-Based CTDSM MEA Readout IC Achieving High Yield and Reliability Through Slot-Partitioned Channel Redundancy
DOI
Hyeok-Ki Hong, Joonseong Kang, Byungsu Jung, Nahmil Koo, Seong-Joong Kim, Hankyu Lee, Dong-Jin Chang, Mikyung Kim, Junyeub Suh, Jonghan Kim, Takhyung Lee, Anes Ju, Jaechun Lee, Chang-Woo Shin, Kitae Park, Chisung Bae

Samsung · Samsung · Dankook University · Chungnam National University
JSSC
2026

A Three-Stacked Switchable Hybrid-Shutter CMOS Image Sensor With 1.2- μ m-Pitch 50-Mpixel Rolling Shutter and 2.4- μ m-Pitch 12.5-Mpixel Global Shutter Modes for Mobile Applications
DOI
Heesung Shim, Seung-Sik Kim, Min-Woong Seo, Sangsu Park, Hyukbin Kwon, Yongjun Kim, Sanggwon Lee, Haeyong Park, Daehee Bae, Si Gyoung Koo, Masamichi Ito, Jae-Hoon Jeon, Sol Yoon, Sung-Jae Byun, Sangyoon Kim, KwanSik Kim, Gihwan Cho, Su-Hyun Han, Joonho Lee, Tekyou Kim, Sungjae Jun, Jae-Kyu Lee, Jonghyun Go, Jaihyuk Song

Samsung
JSSC
2026

An Eight-Channel, 42-Gb/s/Channel Single-Ended PAM-4 Transmitter With a ZQ-Based FFE and PAM-4 LSB DBI Encoding for Memory Interfaces
DOI
Yonghwa Kwon, Geunyoung You, Yunseong Jo, Hyuntae Kim, Young Choi, Jaewoo Park, Myoungbo Kwak, Jaeduk Han

Hanyang University · Samsung
JSSC
2026

Cache-PIM: An ECC-Compatible eDRAM Processing-in-Memory for Last-Level Cache With Triple-Level Error Correction
DOI
Sangwoo Ha, Soyeon Um, Sangjin Kim, Kyomin Sohn, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2026

Falcon: Event-Driven Hybrid Object Tracking SoC With Bit-Column-Similarity-Based MRAM PIM and Heterogeneous Read-Only-Once Attention Flow
DOI
Wenao Xie, Haoyang Sang, Zhamaliddin Kalzhan, Jingu Lee, Jerald Yoo, Kangho Lee, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · University of Macau · Seoul National University · Samsung
JSSC
2026

Human Limb ExG Monitoring System Using Four-Node Body Channel Communication With Adaptive Gain Control
DOI
Song-I Cheon, Dongyoon Lee, Hyungjoo Cho, Seonghyun Park, Sohmyung Ha, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · New York University Abu Dhabi · New York University
VLSI
2026

A 12 V-to-1V Scalable 2N-Phase Buck Converter Using 0V-Stress Balancer with Shortest $I_{\mathrm{L}}$ Balancing Path for Parallel IC Expansion in xPU Systems
DOI
Young-Jun Jeon, Chan-Ho Lee, Jong-Woo Jang, Sung-Wan Hong

Sogang University · Samsung · Seoul National University
VLSI
2026

A 16 Mb 28 nm FD-SOI STT-MRAM Achieving 2.0 ns Read Access Time at 0.9 V via a PVT-Variation-Tolerant Dual-Reference Sensing Scheme
DOI
Donguk Seo, Youjin Choi, Mingyu Kim, Heeyeon Kim, Kyungjun Lee, Jaerok Kim, Donggyu Kim, Shin Han, Yoonmyung Lee

Sungkyunkwan University · Samsung
VLSI
2026

A 1V Time-Division-Multiplexed 4-Channel 3 ${ }^{\text{rd}}$-Order NS-SAR ADC with 178.8dB FoM $\mathrm{M}_{\text{DR}}$ and $\text{5.8G} {\Omega}$ Input Impedance for Wearable Dry-Contact Biopotentials
DOI
Geunha Kim, Sehwan Lee, Taeryoung Seol, Kyuhyeon Park, Jeongyoon Wie, Minoo Lee, Seokhan Jeong, Yeonjae Shin, Sangkyu Lee, Byeongwoo Koo, Michael Choi, Junghyup Lee

Daegu Gyeongbuk Institute of Science and Technology · Samsung · Georgia Institute of Technology
VLSI
2026

A 20T Low-Power Single-Phase Full-Static Contention-Free Flip-Flop with Interlatch Transistor Sharing
DOI
Minkyu Ko, Bomin Joo, Byeonggon Kang, Unbok Wi, Jieun Kim, Dalhee Lee, Changbeom Kim, Hayoung Kim, Sanghoon Baek, Bai-Sun Kong

Sungkyunkwan University · Samsung · University of California San Diego
VLSI
2026

A 3200×2880, 120Hz OLED Display Driver IC with Miller-Charge Cancellation (MCC) Achieving a $\text{13.3V} {/} {\mu}\mathrm{s}$ Slew Rate Under Worst-Case Full-Channel Load
DOI
Suyun Chae, Taeksu Kwon, Yousung Park, Insuk Kim, Yeongmin Kim, Siwoo Kim, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
VLSI
2026

A 6.78MHz Fractional-Resonance Full-Wave Current-Mode Wireless Receiver with Real-Time SAR-Based Optimum Tracking and Power-Aware Division Control
DOI
Jong-Hun Kim, Seong-Ju Lee, Seogyong Jeong, Mun-Jung Cho, Yeon-Woo Jeong, Min-Sik Kim, Myeong-Ho Kim, Dong-Chan Lee, Min-Gyu Jeong, Geon Kim, In-Hye Hur, Eun-Jae Ko, Se-Un Shin

Pohang University of Science and Technology · Samsung
VLSI
2026

A Floating-Inverter Integrator LDO Achieving Near-Zero Line Regulation via Parasitic-Synthesized Supply-Tracking Offset
DOI
Jaehoon Lee, Yeji Min, Jae-Yoon Sim

Samsung · Pohang University of Science and Technology
VLSI
2026

A Scalable Distributed Digital LDO Achieving Fast and Accurate Current Balancing
DOI
Sang-Yun Nam, Won-Gyu Kim, Jaeseung Lee, Jun-Hyeok Yang, Sung-Wan Hong

Sogang University · Samsung · Seoul National University
VLSI
2026

An 11B Source-Driver IC with Resistor-Resistor-Embedded (RRE) DAC and Multi-Step Offset Calibration Achieving 1723 µm 2 /Channel and 1.6 mV DVO for 6285-PPI OLED-On-Silicon Displays
DOI
Chong-Hwa Bae, Hyeon-Ho Park, Wiman Yoo, Junghwan Oh, Dong-Hyun Kim, Gang-Bae Park, Mungyu Kim, Chankeun Kwon, Dongwan Ha, Jong-Seok Kim

Hanyang University · Samsung
VLSI
2026

An 80.198um 2 Compact TRNG with Bias Mitigation, Proven PVT Tolerance in 4nm
DOI
Yunhyeok Choi, Yong Ki Lee, Bohdan Karpinskyy, Jieun Park, Hyunwoo Ko, Yongsoo Kim, Taewook Park, Jisu Kang, Sungha Lee, Gapkyung Kim, Jonghoon Shin, Hyo-Gyuem Rhew

Samsung
VLSI
2026

An IEEE 802.15.4z-Compliant IR-UWB System-on-Chip with 27 dB Self-Interference Cancellation and Reconfigurable TIA for Automotive Radar and Ranging
DOI
Hyun-Gi Seok, Sinyoung Kim, Wonjun Jung, Junhyeong Kim, Eunhye Park, Yeongdae Kim, Jaekeun Lee, Sumin Kang, Jonghoon Myeong, Duyong Seo, Honggul Han, Hyeonuk Son, Junyoung Jang, Hoon Kang, Chiyoung Ahn, Hyukjun Sung, Wan Kim, Hyun-Chul Park, Chan-Hong Park, Joonsuk Kim

Samsung
VLSI
2026

Dual-Phase Offset Compensation and Conditional Latch Gating for a Fully Singleended Dram Core Data-Line Architecture Operating at 0.75 V
DOI
Chang-Young Lee, Young-Seok Park, Hyeon-Jin Park, Dong-Hak Shin, Keon-Woo Park, Se-Ryeong Yoon, Dong-Kyu Lee, Min-Soo Kim, Gi-Jong Sung, Kyu-Chang Kang, Sang-Yun Kim, Hyun-Chul Yoon, Bok-Yeon Won, In-Cheol Nam, Young-Hun Seo, Seung-Jun Bae, Young-Soo Sohn, Sang-Jun Hwang

Samsung
VLSI
2026

Robust Configurable 1.5 MHz/2.5 MHz IF Quadrature CT ΔΣ Modulator Using SAQB and QDNC for 175.4 dB FoMs in 14 Nm FinFET
DOI
Seong-Eun Cho, Ye-Dam Kim, Jongmi Lee, Yong Lim, Yong-Sik Kwak, Kyoung-Jun Moon, Sangmin Yoo

Samsung
A-SSCC
2025

A 1024-Channel VCO-Based CTDSM Neural Readout IC with Slot-Level Channel Replacement
DOI
Hyeok-Ki Hong, Joonseong Kang, Byungsu Jung, Nahmil Koo, Seong-Joong Kim, Hankyu Lee, Dong-Jin Chang, Mikyung Kim, Junyeub Suh, Jonghan Kim, Takhyung Lee, Anes Ju, Jaechun Lee, Chang-Woo Shin, Kitae Park, Chisung Bae

Samsung · Samsung · Dankook University · Chungnam National University
A-SSCC
2025

A 250kHz-BW 86.2dB-SNDR 176.7dB-FoMS Fully Dynamic kT/C Noise-Canceled DT DSM with SAR-Assisted Input FF and DNC
DOI
Young-Hun Moon, Kun-Woo Park, Kyunghoon Kim, Minho Kwon, Min-Jae Seo, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung · University of Seoul
A-SSCC
2025

A 28nm 77.2 TFLOPS/W Digital Floating-Point Compute-InMemory Macro Employing Dynamic Find-Max and ReducedCycle Bit-Serial Architecture with Approximation
DOI
Jaerok Kim, Heeyeon Kim, Yoonmyung Lee

Sungkyunkwan University · Samsung
A-SSCC
2025

A 31.88 A /mm 2 Digital Power Delivery with Surrounding Pass-gates Architecture based on Directional-Selective Nested Quadrant Section Control in 28nm CMOS
DOI
Wonae Park, Junyeop Kim, Yuli Han, Gunmo Koo, Joo-Young Kim, Kunhee Cho

Sungkyunkwan University · Seoul National University · Korea Advanced Institute of Science and Technology · Samsung
A-SSCC
2025

A 4-24 Gb/s/wire Single-Ended NRZ Die-to-Die Transceiver with Low Latency for UCle Standard Package in 4nm FinFET
DOI
Jisu Yook, Jahoon Jin, Younggyun Oh, Soo-Min Lee, Kyunghwan Min, Cheolhwan Lim, Woongki Min, Seungjun Lee, Myung-Cheol Kim, Jinhun Park, Sungsik Park, Hiep Pham, Wanghua Wu, Xinglian Zhao, Chih-Wei Yao, Qilin Gu, HyojunKim, Sangho Kim, Sangmin Yoo

Samsung
A-SSCC
2025

A 6.5-to-12.5Gb/s Reference-Less Dual-Loop CDR with Adaptive Injection Gain Switching and Self-aligned Injection Phase Detection in 28nm CMOS
DOI
Minsu Park, Jahoon Jin, Sangdon Jung, Hyunki Park, Jung-Hoon Chun

Sungkyunkwan University · Samsung
A-SSCC
2025

A 7-level 18-wire-state Trio-signaling Transmitter for MIPI C-PHY 3.0 Interfaces
DOI
Myeongjin Oh, Junyeong Lee, Kiwoon Kim, Jung-Hoon Chun

Samsung · Sungkyunkwan University
A-SSCC
2025

Wideband linearity enhancement technique using Source Follower (SF) feedforward distortion cancellation with GaN technology
DOI
Jungyeon Jo, Deokyoung Kim, Sanghun Lee, Tae Wook Kim

Yonsei University · Samsung
CICC
2025

A Phase-Locked Minimum-Energy-Point-Tracking Enabled by Unified-Clock-Power-and-Body-Bias Slack Regulation and PI-Ratio Based In-Situ Loop Gain Optimization with 97.4% Supply Voltage Margin Recovery at Minimum-Energy-Point in 28nm FDSOI
DOI
Minhyeok Jeong, Hyungmin Gi, Minsik Cho, Mingyu Kim, Donggyu Kim, Sungyong Park, Woonjae Lee, Seonho Kim, Yeohoon Yoon, Shin Han, Donguk Seo, Jongmin Lee, Yoonmyung Lee

Sungkyunkwan University · Samsung · Hyundai Motor Group (South Korea) · Ajou University
CICC
2025

An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface
DOI
Giyeong Heo, Younghwan Chang, Yong-Un Jeong, Jaekwang Yun, Jusung Lee, Shin-Hyun Jeong, Sanghyuk Seo, Suhwan Kim

Seoul National University · Samsung · Sejong University
CICC
2025

Demonstration of Logic-Block Performance-Power-Area Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node
DOI
H. Fukutome, J. Kim, J. Shin, J. Kim, Y. Lee, S. Chae, B. Eom, Y.S. Nam, M. Lee, S. Ha, E.G. Chung, S.H. Lee, S. Kim, K.H. Cho, K.W. Lee, D.-W. Kim, H.-J. Cho, K. Rim, J. Song

Samsung
ESSERC
2025

A 12-to-20Gb/s, 2.93-pJ/Bit Jitter-Filtering Retimer with High Input Jitter Tolerance in 28nm CMOS
DOI
Inhyun Kim, Hyeonseok Lee, Ankur Kumar, Mingi Yeo, David Dolt, Taeyang Sim, Seongkwan Lee, Cheolmin Park, Minho Kang, Jun Yeon Won, Jaemoo Choi, Jaeduk Han, Samuel Palermo

Texas A&M University · Samsung · Hanyang University
ESSERC
2025

A 6.0 TOPS/W Reconfigurable AI-Based Channel State Information Compression Using Delta Encoding in Multi-Receiver Mobile Systems
DOI
Hana Kim, Zihan Xia, Yuchan Li, Suraj P N, Rishabh Kumar, Pranav Raj, Hyunseok Lee, Junho Lee, Jiyong Yoon, Jungwon Lee, Ji-Hoon Kim, Mingu Kang

University of California San Diego · Samsung · Hanyang University
ESSERC
2025

A 7b 30GS/s 0.032mm 2 CI-SAR TIADC in 28-nm CMOS with Fractional-Delay FIR Filter Based Full-Digital Background Timing Skew Calibration
DOI
Jongho Kim, Gyuchan Cho, Hwankyu Song, Hyeonsik Kim, Jintae Kim

Samsung · Konkuk University
ESSERC
2025

A 97% Peak-Efficiency Dual-Channel 3-Fine-Level Buck-Boost Converter with Capacitive Inrush Current Reduction and Seamless Mode Transition Using a Slim 0.65-Thickness Inductor
DOI
Minsu Kim, Hyunjun Park, Yunho Lee, Hongseok Kim, Woojoong Jung, Minwoo Kim, Junhyun Bae, Hyoung-Seok Oh, Hwayeal Yu, Hyung-Min Lee

Korea University · Samsung
ESSERC
2025

Falcon: An Event-Driven Object Tracking SoC with Activation-Skip and Weight-Compression MRAM PIM and Heterogenous Q/K/V Read-Only-Once Attention Flow
DOI
Wenao Xie, Haoyang Sang, Zhamaliddin Kalzhan, Jingu Lee, Jerald Yoo, Kangho Lee, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Seoul National University · Samsung
ISSCC
2025

10.4 A 2- TRX IR-UWB Transceiver with Shared Antennas Supporting Channels 5 to 12 in Compliance with IEEE 802.15.4/4z Standards
DOI
Hyun-Gi Seok, Jaekeun Lee, Sinyoung Kim, Wonjun Jung, Honggul Han, Junhyeong Kim, Sumin Kang, Chanho Kim, Wonkang Kim, Jongpil Cho, Seungyoung Bae, Yanghoon Lee, Sungbeom Kim, Hyeonuk Son, Junyoung Jang, Taeyeon Kim, Sanguk Cho, Misuk Cho, Chiyoung Ahn, Hyukjun Sung, Wan Kim, Seunghyun Oh, Jongwoo Lee, Hyungjong Ko, Joonsuk Kim

Samsung
ISSCC
2025

16.3 An on-Device Generative AI Focused Neural Processing Unit in 4nm Flagship Mobile SoC with Fan-Out Wafer-Level Package
DOI
Jun-Seok Park, Taehee Lee, Heonsoo Lee, Changsoo Park, Youngsang Cho, Mookyung Kang, Heeseok Lee, Jinwon Kang, Taeho Jeon, Dongwoo Lee, Yesung Kang, Kyungmok Kum, Geunwon Lee, Hongki Lee, Minkyu Kim, Suknam Kwon, Sung-beom Park, Dongkeun Kim, Chulmin Jo, HyukJun Chung, Ilryoung Kim, Jongyoul Lee

Samsung
ISSCC
2025

21.6 A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC
DOI
Jeong-Hun Kim, Young-Jun Jeon, Won-Gyu Kim, Jaeseung Lee, Jun-Hyeok Yang, Sung-Wan Hong

Sogang University · Samsung
ISSCC
2025

22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding
DOI
Yunseong Jo, Hyuntae Kim, Young Choi, Jaewoo Park, Myoungbo Kwak, Jaeduk Han

Hanyang University · Samsung
ISSCC
2025

30.1 A 28Gb/mm24XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs
DOI
Sang-Soo Park, Jae-Doeg Lyu, Myungjun Kim, Jaeyun Lee, Younsun Song, Chung-Ho Yu, Hirano Makoto, Yongseok Kwon, Jong-Hoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Byungrok Go, Seoyoon Jeon, Yoonjee Kim, Doo-Hyun Kim, Youngmin Jo, Hyunjun Yoon, Junehong Park, Inmo Kim, Sunghoon Kim, Hokil Lee, Je-Hyeon Yu, Sang-Lok Kim, Hwan-Seok Ku, Jungmin Seo, Jindo Byun, Seung-Hyeon Yun, Kyoungtae Kang, Seung-Beom Kim, Yohan Lee, Yongkyu Lee, Kyunghwa Kang, Han-Jun Lee, Younghwan Ryu, Hyundo Kim, Wontae Kim, Hyeongdo Choi, Juho Jeon, Ansoo Park, Raehyun Song, Jae-Hwan Kim, Jung-Soo Kim, Hwa-Seok Lee, Moo-Kyung Lee, Jae-Ick Son, Jiho Cho, Moosung Kim, Jae-Woo Im, Jongmin Park, Hyuckjoon Kwon, Youngdon Choi, Chiweon Yoon, Seungjae Lee, Kiwhan Song, Sung-Hoi Hur

Samsung
ISSCC
2025

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction
DOI
Sang-Hoon Kim, Jaehyeok Baek, Moon-Chul Choi, Daewoong Lee, Donggun An, Se mi Kim, Yeonggeun Song, Minkyo Shim, Sung-Yong Cho, Dongha Lee, Gunhee Cho, In-Woo Jun, Juseop Park, TaeYoon Lee, Hwan-Chul Jung, Chanyong Lee, Gil-Young Kang, Hye-Ran Kim, Jongmyung Lee, Young Su Joo, Hyo-Jin Jung, Bokyeon Won, Ji-Hak Yu, Sangkeun Han, Yechan Hwang, Chungman Kim, Seok-Jung Kim, YoungSeok Lee, Young-Tae Kim, Myeong-O Kim, Wonhwa Shin, Tae-Young Oh, SangJoon Hwang

Samsung
ISSCC
2025

37.3 Monolithic in-Memory Computing Microprocessor for End-to-End DNN Inferencing in MRAM-Embedded 28nm CMOS Technology with 1.1Mb Weight Storage
DOI
Soonwan Kwon, Sungmeen Myung, Jangho An, Hyunsoo Kim, Minje Kim, Hyungwoo Lee, Wooseok Yi, Seungchul Jung, Daekun Yoon, Shinhee Han, Saeyoon Chung, Kilho Lee, Jeong-Heon Park, Kangho Lee, Sang Joon Kim, Donhee Ham

Samsung · Samsung
ISSCC
2025

5.4 A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplifier with a Stacked OPA-Based Bias Scheme Achieving >16.5dBm Pavg for 5G FR2 Applications
DOI
Jooseok Lee, Hansik Oh, Seungjae Baek, Seungwon Park, Dongsoo Lee, Sehyug Jeon, Taewan Kim, Joonho Jung, Sung-gi Yang

Samsung
ISSCC
2025

6.1 A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable $1.2\mu\mathrm{m}$ -Pitch 50Mpixel Rolling Shutter and $2.4\mu\mathrm{m}$ -Pitch 12.5Mpixel Global Shutter Modes for Mobile Applications
DOI
Heesung Shim, Seung-Sik Kim, Min-Woong Seo, Sangsu Park, Hyukbin Kwon, Yongjun Kim, Sanggwon Lee, Sungbong Park, Daehee Bae, Si Gyoung Koo, Masamichi Ito, Jae-hoon Jeon, Sol Yoon, Sung-Jae Byun, Sangyoon Kim, KwanSik Kim, Gihwan Cho, Joonho Lee, Tekyou Kim, Sungjae Jun, Jae-kyu Lee, Chang-Rok Moon, Jaihyuk Song

Samsung
ISSCC
2025

8.4 A 4GHz, 0.69%-Accuracy Voltage-Droop Detector with Multiple Remote Sensing and Under 2-Cycle Detection Latency in 2nm GAAFET
DOI
DongHoon Jung, Dongha Lee, Seki Kim, Susie Kim, Min Young Kang, Takahiro Nomiyama, Dongsu Kim, Jongwoo Lee

Samsung
ISSCC
2025

9.8 A 50W 98%-Efficiency High-Power Wireless-Charging System with an Acoustic Noise-Reduced Ask Modulation Technique and Internal Hybrid Voltage-/Current-Mode ASK Demodulation
DOI
Seongjin Oh, Hansol Kim, Hyunsu Kim, Gyeongho Namgoong, Woojin Park, Sangbeom Heo, Jaekyu Kim, Sungwoo Moon, Hyoung-Seok Oh, Hwayeal Yu

Samsung
ISSCC
2025

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process
DOI
Jin-Hyeok Baek, Jang-Hoo Kim, Yoo-Chang Sung, Jae-Woo Jeong, Jin-Kwan Park, Hyun-Kyu Oh, Bo-Hyeon Lee, Dong-Wan Ko, Tae-Seob Oh, Seung-Gi Hong, Chang-Ki Kwon, Daihyun Lim, Myeong-O Kim, Seung-Jun Bae, Tae-Young Oh, Sang-Jun Hwang

Samsung
ISSCC
2025

A Compact 10b Source Driver IC with Delta-Sigma Pulse Width Modulation for Low-Voltage Digital Interpolation Achieving 1884μm2/Channel
DOI
Jun Yeol An, Seung Hun Choi, Jaewoong Ahn, Seunghoon Baek, Youngmin Kim, Si-Woo Kim, Jae-Yeol Lee, Yoon-Kyung Choi, Hyung-Min Lee

Korea University · Samsung
ISSCC
2025

A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCF Balancing and Wide VCR for Foldable Mobile Applications
DOI
Woojin Hong, Hyebong Ko, Jinwoo So, Woonhyung Heo, Yonghwan Cho, Jeongdu Yoo, Ho-Sung Son, Youngwoo Chung, Dong-Joon Kim, Youngwoo Park, Byeonghyeon Jin, Sungkyu Cho, Minkyu Kwon, Kyungmin Park, Daewoong Cho, Jung Wook Heo, Sungwoo Lee, Sungwoo Moon, Hyoung-Seok Oh, Hwayeal Yu

Samsung
ISSCC
2025

AI Revolution Driven by Memory Technology Innovation
DOI
Jaihyuk Song

Samsung
ISSCC
2025

An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies
DOI
Bohdan Karpinskyy, Yong Ki Lee, Sumin Noh, Yunhyeok Choi, Jieun Park, Jisu Kang, Taewook Park, Eunhye Oh, Gapkyung Kim, Sungha Lee, Hyunwoo Ko, Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin

Samsung
ISSCC
2025

An Enhanced-Frequency-Splitting-Based Wireless Power and Data Transfer System Achieving 60.2% End-to-End Efficiency and 1 Mb/s Data Rate with a Sub-cm RX Coil for Miniaturized Implants
DOI
Yechan Park, Phan Dang Hung, Donghyun Youn, Daehyeon Kwon, Chul Kim, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2025

100–112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology
DOI
Eunji Song, Jeonghyu Yang, Youngmin Oh, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han

SK Group (United States) · SK hynix · Hanyang University · Samsung
JSSC
2025

A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS
DOI
Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2025

A 0.5–1-V Time-Voltage Hybrid Domain Dual- Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm
DOI
Jun-Hwan Jang, Hui-Dong Gwon, Sungmin Yoo, Jun-Hyeok Yang, Byong-Deok Choi

Hanyang University · Samsung
JSSC
2025

A 10-V-Tolerant Dual-Mode Neural Stimulation System With Self-Sustaining Dynamic Supply and Error-Resilient Digital Stimulus Odometer
DOI
Kyeongho Eom, Han-Sol Lee, Seung-Beom Ku, Joonghoon Kang, Hyungjin Jung, Taewoo Kim, Jaesoon Joo, Taekyung Kim, Young-Min Shon, Hyung-Min Lee

Korea University · Samsung · Sungkyunkwan University
JSSC
2025

A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator
DOI
Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi

Korea Advanced Institute of Science and Technology · Samsung · Qualcomm · Seoul National University
JSSC
2025

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology
DOI
Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo

SK hynix · Hanyang University · Korea Electronics Technology Institute · Samsung · Gachon University · Seoul National University · Yonsei University
JSSC
2025

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration
DOI
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-Hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Un-Hak Lim, Hongjun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Won Ju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Tae-Hoon Park, Changsik Yoo, Tae-Young Oh, SangJoon Hwang

Samsung
JSSC
2025

A 27–39-GHz VSWR-Resilient Compact True Power and Gain Sensor With Built-In Sensing Error Compensation for Integrated Power Amplifiers
DOI
Edward Liu, David Munzer, Jeongseok Lee, Jianping Zeng, Hua Wang

ETH Zurich · Georgia Institute of Technology · Samsung
JSSC
2025

A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine V CF Balancing and Frequency Foldback Control for Foldable Mobile Applications
DOI
Woojin Hong, Hyebong Ko, Jinwoo So, Woonhyung Heo, Yonghwan Cho, Jeongdu Yoo, Ho-Sung Son, Youngwoo Chung, Dong-Joon Kim, Byeonghyeon Jin, Minkyu Kwon, Kyungmin Park, Daeyong Han, Sungkye Cho, Daewoong Cho, Jung Wook Heo, Sungwoo Lee, Sungwoo Moon, Hyoung-Seok Oh, Hwayeal Yu

Samsung
JSSC
2025

A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15 Gb/s for TSV Interface
DOI
Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung Mo Moon, Kyomin Sohn, Seong-OoK Jung

Yonsei University · Samsung
JSSC
2025

A Single-Duty-Cycled Buck-Boost Converter Achieving Low Output Ripple and Seamless Mode Transition
DOI
Jae-Hyun Kim, Yousung Park, Doyoung Kwon, Dae-Hyeon Kim, Dong-Kyu Kim, Sung-Chun Park, Yongjae Lee, Jung-Bong Lee, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2025

An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory
DOI
Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee

Korea University · Seoul National University · Samsung · Samsung
JSSC
2025

An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth
DOI
Junghyun Yoon, MoonHyung Jang, Changuk Lee, Yong Lim, Youngcheol Chae

Yonsei University · Stanford University · University of California, Berkeley · Samsung
JSSC
2025

An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier
DOI
Kyeongtae Nam, Dongil Lee, Kyuchang Kang, Sang-Yun Kim, Changyoung Lee, Hyunchul Yoon, Donggeon Kim, Bokyeon Won, Jae-Joon Song, Jaehyuk Kim, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang

Samsung
JSSC
2025

Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI
DOI
Seongyon Hong, Wooyoung Jo, Sangjin Kim, Sangyeob Kim, Soyeon Um, Kyomin Sohn, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2025

ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM
DOI
Wenao Xie, Haoyang Sang, Beomseok Kwon, Dongseok Im, Sangjin Kim, Sangyeob Kim, Kangho Lee, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2025

High-Sensitivity, Low-Power IR-UWB Radar Transceiver With Self-Interference Resistance for Child Presence Detection and Precision Positioning
DOI
Hyun-Gi Seok, Wan Kim, Sinyoung Kim, Jae-Keun Lee, Geunhaeng Lee, Chanho Kim, Wonkang Kim, Jongpil Cho, Seungyong Bae, Youngsea Cho, Wonjun Jung, Junhyeong Kim, Sumin Kang, Hyeokju Na, Byoungjoong Kang, Honggul Han, Hoon Kang, Chiyoung Ahn, Sukjin Jung, Hyukjun Sung, Seunghyun Oh, Jongwoo Lee, Joonsuk Kim

Samsung · Incheon National University
JSSC
2025

Mixed-Order Correlated Dual-Loop Sturdy MASH CT-ΔΣ Modulator With Distributed Signal Feed-In and VCO Quantizer
DOI
Xiaodong Xu, Beomsoo Park, Marino Guzman, Yingjie Chen, Changsok Han, Nima Maghari

University of Florida · Qualcomm · Texas Instruments · Samsung
VLSI
2025

A 1.22 e-rms Temporal Random Noise, 110 dB High Dynamic Range, 2.988 \mu\mathrm{m}$ Pixel-Pitch 3-Stacked Digital Pixel Sensor with On-Chip HDR Merger
DOI
Min-Woong Seo, Yong-Suk Choi, Sanggwon Lee, Masamichi Ito, Daehee Bae, Yeongseok Shim, Gihwan Cho, Si-Gyoung Koo, Sung-Jae Byun, Hyukbin Kwon, Suksan Kim, KwanSik Kim, Youna Lee, Bumjun Kim, Jaehun Jeong, Hiroyuki Sugihara, Su-Hyun Han, Sangsu Park, Yongjun Kim, Heesung Shim, Seung-Sik Kim, Jae-kyu Lee, Jonghyun Go, Jaihyuk Song

Samsung
VLSI
2025

A 1.2Mp 2.8 um 4-tap Indirect Time-of-Flight Sensor with 42% Quantum Efficiency at 940 nm Wavelength with Enhanced Angular Response
DOI
Seunghyun Lee, Minhee Son, Sungyoung Seo, Sunghyuck Cho, Young-Gu Jin, Youngsun Oh, Seunghyun Song, Seok-Ha Lee, DaeHan Han, Daeho Kim, Minsik Kim, Il-Pyeong Hwang, Youngkyun Jeong, Daeyun Kim, Min-Sun Keel, Juhyun Ko, Howoo Park, Kyungho Lee

Samsung
VLSI
2025

A 1.7 pJ/bit 10 MHz Calibration-Free PVT Variation and Mismatch Tolerant Latch-Based True Random Number Generator in 4 nm FinFET
DOI
Jaehoon Lee, Jongmi Lee, Yelim Youn, Yong Lim, Dongyeon Hong, Bogyeong Kang, Sangmin Yoo, Jae-Yoon Sim

Pohang University of Science and Technology · Samsung
VLSI
2025

A 12-Gb/s Single-Ended Transmitter with Echo-Canceling FFE for Multi-Drop Bus in 28Nm CMOS
DOI
KuyYoun Chung, Yubin Kim, DongArm Shin, SeongHwan Cho

Korea Advanced Institute of Science and Technology · Samsung
VLSI
2025

A 12-Mpixel Automotive Image Sensor with 137-dB Single-Exposure Dynamic Range and 0.55-Electron Read Noise by Oversampling-Based Noise Reduction
DOI
Min-Sun Keel, Kyung-Min Kim, Haneol Seo, Seok-Yong Park, Mira Lee, Donghyun Kim, Jeonga Jo, Jonghyuk Woo, Youngtae Jang, Jinkyeong Heo, Jungwook Lim, Dongsuk Yoo, Soeun Park, Youngsun Oh, Youngkyun Jeong, Bumsuk Kim, Kyungho Lee, Juhyun Ko, Haechang Lee, Jesuk Lee

Samsung
VLSI
2025

A 212.5Gb/s Pam-4 Receiver With Mutual Inductive Coupled Gm-Tia in 4nm Finfet
DOI
Kibaek Kwon, Hyungdong Roh, Kihong Kim, Dongin Noh, Woongtaek Lim, Joonkyung Park, Dokyung Lim, Dohun Jang, Punghwan Lim, Jaehong Do, Subin Yim, Dong-Hyuk Lim, Byoung-Joo Yoo, Michael Choi, Hyo-Gyuem Rhew, Jongshin Shin

Samsung
VLSI
2025

A 2Nm Gate-All-Around 128Kb Anti-Fuse One-Time Programmable Memory Featuring Dynamic Bit-Line and Sense-Amplifier Offset Cancellation
DOI
Sangmin Shin, Jaehyung Sin, Jisoo Lee, Gyutae Kwon, Sangseok Lee, Kun Jae Lee, Sewon Ki, Hyojoon An, Mijoung Kim, Hoonjin Bang, Jonghoon Jung, Sanghoon Baek

Samsung
VLSI
2025

A 4.2 Gb/S $5^{\text {th }}$ Generation F-Chip of Toggle 5.1 Specification With All-Path Speed Boosting Scheme and Sca Protocol for High Density Nand Flash Applications
DOI
Kyeonghwan Park, Jichull Jeong, Seung-Jin Park, Doobock Lee, Seunghoon Lee, Soonku Kang, Youngmin Kang, Soomin Ko, Yongjin Kim, Jun-Ho Boo, Mingyu Lee, Eunsang Lee, Geoeun Cha, Youngmin Kim, Jisun Lee, Seungwan Kang, Inbok Cho, Minjae Lee, Yongmin Kim, Seol-Jun Go, Moon-Ki Jung, Kisung Kim, Eung Suk Lee, Youngmin Jo, Jung-June Park, Chiweon Yoon, Myoungbo Kwak, Hwaseok Oh, Soonjae Won

Samsung
VLSI
2025

A 90–260 $\mathrm{V}_{\text{AC}}$ Isolated Offline Single-Stage Single-Transformer-Winding Multiple-Output (STWMO) RGBW LED Driver with <0.7% Current Variation and Dimmable Current-Regulated Error-Based Control
DOI
Mun-Jung Cho, Changsik Shin, Seung-Ju Lee, Jong-Hun Kim, Yeon-Woo Jeong, Min-Sik Kim, Myeong-Ho Kim, Hyuntak Jeon, Se-Un Shin

Pohang University of Science and Technology · Samsung · Chungbuk National University · Jeonbuk National University
VLSI
2025

A Hybrid Touch Sensing AFE with Common-CVQ (Currents, Voltages, and Charges) Subtraction to Improve Display Noise Immunity for Large Sensing Load up to 820pF
DOI
Seung Hun Choi, Jun Yeol An, Jaewoong Ahn, Jae-Youl Lee, Si-Woo Kim, Hyung-Min Lee, Yoon-Kyung Choi

Korea University · Samsung
VLSI
2025

Dial: An Energy-Efficient Dram in-Memory Computing Accelerator with Compact Partial Product Lut and Twisted Differential Adc
DOI
Soyeon Um, Sangwoo Ha, Sunjoo Whang, Minsung Kim, Byeongcheol Kim, Sangjin Kim, Junha Ryu, Chaeyun Jeong, Kyomin Sohn, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung
A-SSCC
2024

A 0.036mm 2 80Mb/s-to-15.96Gb/s C-PHY and D-PHY Combo Receiver with Background Calibrations in 4nm FinFET
DOI
Woongki Min, Soomin Lee, Taejin Jang, Yunsik Jo, Hyoungjoong Kim, Younggyun Oh, Myeong-Cheol Kim, Hyeonji Han, Cheolhwan Lim, Seungjun Lee, Jihoon Lee, Yon Jun Shin, Sangho Kim, Jongwoo Lee

Samsung
A-SSCC
2024

A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application
DOI
Young-Gil Go, Hyun-A Ahn, Yoo-Chang Sung, Myung-Hun Jung, Ji-Geon Yeom, Hun-Dae Choi, Janghoo Kim, Hyunjin Ko, Miyoung Woo, Seong-O Huh, Seung-Jun Bae, Tae-Young Oh

Samsung
A-SSCC
2024

A 1.27-mW Battery-Powered Multimodal Biosensor Interface IC for Wireless Motion Intention Recognition in Wearable Robots
DOI
Jimin Koo, Haidam Choi, Yoontae Jung, Ji-Hoon Suh, Sein Oh, Changhun Seok, Yegeun Kim, Injun Choi, Heewon Choee, Sunglim Han, Jiho Chun, Hoyong Seong, Sohmyung Ha, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · SK hynix · New York University Abu Dhabi
A-SSCC
2024

A 10.5 Gbps 0.55 pJ/bit PAM-3 Transceiver Using a Self-driven Dual TIA Receiver and Floating Impedance Matching for Parallel On-chip Transmission Lines
DOI
Donghyun Yoon, Junsen He, Kwang-Hyun Baek, Youngdon Choi, Junghwan Choi, Tony Tae-Hyoung Kim

Nanyang Technological University · Chung-Ang University · Samsung
A-SSCC
2024

A 105.8dB A-weighted DR CT Delta-Sigma Audio ADC Using Current-Steering DAC Current Recycling Amplifier
DOI
Moo-Yeol Choi, Myungjin Lee, Minsung Kim, Dongsu Kim, Jongwoo Lee

Samsung
A-SSCC
2024

A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology
DOI
Hong-Seok Choi, Jae-Geon Lee, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyung-Rok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Min-Seong Choo

SK hynix · Hanyang University · Korea Electronics Technology Institute · Samsung · University of Suwon · Seoul National University
A-SSCC
2024

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module
DOI
Joomyoung Kim, Jaehong Jung, Kwangmin Lim, Barosaim Sung, Jaekwon Kim, Baekmin Lim, Tae-Gun Noh, Jaehoon Lee, Hyun-Gi Seok, Youngsea Cho, Gyusik Kim, Takahiro Nomiyama, Sunhye Kang, Yeongcheol Jeong, Sanguk Cho, Gyumin Kim, Do-Hyun Oh, Jaenam Kim, Yong Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee

Samsung
A-SSCC
2024

A 28-nm 323 TOPS/mm 2 /b and 2007 TOPS/W/b Ternary Latch Based Sparsity-Aware CIM Macro With Double-Sampling Ternary ADC
DOI
Myoung Kim, Hoichang Jeong, Woo-Seok Kim, Yesong Jeong, Young-Eun Choi, Junyoung Park, Min Woo Ryu, Yong Kyu Lee, Kyuho Jason Lee, Kyung Rok Kim

Ulsan National Institute of Science and Technology · Samsung
A-SSCC
2024

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA
DOI
Bo Gao, Lizhen Zhang, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung
A-SSCC
2024

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM
DOI
Yoonjae Choi, Jaegeun Song, Daero Kim, Myunggon Kim, Jiyeon Park, Jinho Choi, Changki Kwon, Minho Seo, Jihun Oh, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Jongshin Shin

Samsung
A-SSCC
2024

A 45-fs rms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology
DOI
Subhadeep Datta, Arnab Banerjee, Ayush Tripathi, Dongmin Kang, Sunghyuck Lee, Hasung Lim, Wonsik Yu, Kgj Vishnu, Chanyoung Jeong, Sumanth Chakkirala, Avneesh Singh Verma, Sachin Kashyap, Eg Jeevarathinam, Sunil Kumar Pandey, Jongjae Ryu, Sanjeeb Kumar Ghosh

Samsung · Samsung · Samsung
A-SSCC
2024

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM
DOI
Changyoung Lee, Youngseok Park, Hyunchul Yoon, Seryeong Yoon, Donggeon Kim, Bokyeon Won, Junhwa Song, Injae Bae, Jae-Joon Song, Kyuchang Kang, Jaehyuk Kim, Kyungrak Cho, Incheol Nam, Jungdon Ihm, Younghun Seo, Changsik Yoo, Sangjun Hwang

Samsung
CICC
2024

A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOS
DOI
Hong-Hyun Bae, Jeong-Hyun Cho, Kihyun Kim, Seunghwa Shin, Doojin Jang, Jun-Hyeok Yang, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
CICC
2024

An Analog Neuromorphic On-Chip Training System with IGZO TFT-Based 6T1C 367-State Synaptic Memory Achieving 0.99-R2 Linearity and 104-Times Enhanced Retention Time
DOI
Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee

Korea University · Seoul National University · Samsung · Samsung
ESSERC
2024

A 128Gb/s Hybrid DAC-Based PAM-4 Transmitter with Constant 1.2Vppd Output Swing over PVT in 8nm FinFET
DOI
Minsoo Choi, Hiep Pham, Hyojun Kim, Enhan Mai, Haojiang Li, Qilin Gu, Xingliang Zhao, Jeiyoung Lee, Chih-Wei Yao, Sangwon Son

Samsung · Samsung
ESSERC
2024

A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage
DOI
Jungmyung Kang, Keonhee Cho, Sekeon Kim, Giseok Kim, Hyunjun Kim, Dongwook Seo, Sangyeop Baeck, Seiseung Yoon, Seong-Ook Jung

Yonsei University · Samsung
ESSERC
2024

Cache-PIM: An ECC-compatible eDRAM-PIM for Last-Level Cache with Resolution-aware Single-Cycle Voting
DOI
Sangwoo Ha, Soyeon Um, Sangjin Kim, Kyomin Sohn, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung
ISSCC
2024

10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference
DOI
Byeong-Taek Moon, Hyun-Chul Park, Sang-Gug Lee

Korea Advanced Institute of Science and Technology · Samsung
ISSCC
2024

13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets
DOI
Kihwan Seong, Wooseuk Oh, Hyunwoo Lee, Gyeomje Bae, Youngseob Suh, Hyemun Lee, Juyoung Kim, Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park, Byoung-Joo Yoo, Hyo-Gyuem Rhew, Jongshin Shin

Samsung
ISSCC
2024

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5 th -Generation 10nm DRAM Process
DOI
Ikjoon Choi, Seunghwan Hong, Kihyun Kim, Jeong-Sik Hwang, Seunghan Woo, Young-Sang Kim, Cheong-Ryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byong-Wook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, SangJoon Hwang

Samsung
ISSCC
2024

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate
DOI
Wontaeck Jung, Hyunggon Kim, Do-Bin Kim, Tae-Hyun Kim, Namhee Lee, Dongjin Shin, Minyoung Kim, Youngsik Rho, Hun-Jong Lee, Yujin Hyun, Jaeyoung Park, Taekyung Kim, Hwiwon Kim, Gyeongwon Lee, Jisang Lee, Joonsuc Jang, Jungmin Park, Sion Kim, Su Chang Jeon, Suyong Kim, Jung-Ho Song, Min-Seok Kim, Taesung Lee, Byung-Kwan Chun, Tongsung Kim, Young Gyu Lee, Hokil Lee, Soowoong Lee, Hwaseok Lee, Dooho Cho, Sang-Wan Nam, Yeomyung Kim, Kunyong Yoon, Yoonjae Lee, Sunghoon Kim, Jungseok Hwang, Raehyun Song, Hyunsik Jang, Jaeick Son, Hongsoo Jeon, Myunghun Lee, Mookyung Lee, Kisung Kim, Eungsuk Lee, Myeongwoo Lee, Sungkyu Jo, Chan Ho Kim, Jong Chul Park, Kyunghwa Yun, Soonock Seol, Ji-Ho Cho, Seungjae Lee, Jin-Yub Lee, Sung-Hoi Hur

Samsung
ISSCC
2024

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration
DOI
Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gunhee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang

Samsung
ISSCC
2024

14.10 34.7A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS
DOI
Yong-Jin Lee, Woojin Jang, Hong-Hyun Bae, Jeong-Hyun Cho, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
ISSCC
2024

14.6 A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET
DOI
Dongha Lee, Seki Kim, Takahiro Nomiyama, Dong-Hoon Jung, Dongsu Kim, Jongwoo Lee, Sungung Kwak

Samsung
ISSCC
2024

16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm
DOI
Jieun Park, Yong Ki Lee, Karpinskyy Bohdan, Yunhyeok Choi, Jonghoon Shin, Hyo-Gyuem Rhew, Jongshin Shin

Samsung
ISSCC
2024

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS
DOI
Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi Rao, Chang Liu, Meisam Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer Ali, Hyo Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao

Broadcom · Samsung · Peking University
ISSCC
2024

26.3 Noise Immunity in Capacitive Sensing: Single-Ended AFE Design with Common-Current Subtraction for Mutual- and Self-Capacitance Sensing in 390pF Load
DOI
Jun Yeol An, Seung Hun Choi, Si-Woo Kim, Jae-Youl Lee, Hyung-Min Lee, Yoon-Kyung Choi

Korea University · Samsung
ISSCC
2024

3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA’s 0.7V Thin-Gate-Oxide Transistor
DOI
Sangheon Lee, Jinwoo Park, Junsang Park, Sangkyu Lee, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin

Samsung
ISSCC
2024

31.3 A 950ns 0.5-to-5.5V 5G NR RF PA Supply Modulator with Floating Capacitor Control for Symbol Power Tracking
DOI
Ik-Hwan Kim, Jeong-Il Seo, Younghwan Choo, Seungchan Park, Jaeyeol Han, Woosik Kim, Sungyoub Jung, Taehyuk Ko, Dongsu Kim, Jongwoo Lee, Sungung Kwak

Samsung
ISSCC
2024

32.2 A 24.25-to-29.5GHz Extremely Compact Doherty Power Amplifier with Differential-Breaking Phase Offset Achieving 23.7% PAEavg for 5G Base-Station Transceivers
DOI
Hansik Oh, Seungwon Park, Jooseok Lee, Seungjae Baek, Joonho Jung, Taewan Kim, Jinhyun Kim, Woojae Lee, Jae-Hong Park, Kihyun Kim, Dong-Hyun Lee, Sangho Lee, Jeong Ho Lee, Ji Hoon Kim, Younghwan Kim, Sangyong Park, Bohee Suh, Soyoung Oh, Dongsoo Lee, Sehyug Jeon, Juho Son, Sung-Gi Yang

Samsung
ISSCC
2024

4.2 A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal
DOI
Jongsoo Lee, Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo, Beomyu Park, Jeongkyun Woo, Jaeeun Jang, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Byoungjoong Kang, Minchul Kang, Hojung Kang, John Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Hongjong Park, Sangsung Lee, Jeongyeol Bae, Huijung Kim, Joonhee Lee, Sangmin Yoo

Samsung
ISSCC
2024

4.3 A 43mm2 Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 4×4 MIMO with 1K-QAM
DOI
Jeongyeol Bae, Sangsung Lee, Joonggeun Lee, Ikkyun Jo, Heesoo Kim, Kyunghyun Yoon, Taejong Kim, Jiyoung Lee, Myunghun Lee, Jaeseung Lee, Jongmin Jeong, Sungjun Lee, Taewan Kim, Sungjoo Kim, Gwangsik Cho, Duksoo Kim, Sangyun Lee, Pilsung Jang, Euibong Yang, Jeongmin Song, Gwangchun Park, Se-Eun Choi, Juhee Son, Won Ko, Jonghyun Kim, Seong Ho Park, Sangho Lee, Yoonki Lee, Euiyoung Park, Pillseong Kang, Taeyeon Kim, Hyojin Lee, Byungki Han, Joonhee Lee, Jongsoo Lee, Sangmin Yoo

Samsung
ISSCC
2024

6.10 A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation
DOI
DongHyun Kim, Kwansik Cho, Ho-Chul Ji, Minkyung Kim, Junghye Kim, Taehoon Kim, Seungju Seo, Dongmo Im, You-Na Lee, Jinyong Choi, Sunghyun Yoon, Inho Noh, Jinhyung Kim, Khang June Lee, Hyesung Jung, Jongyoon Shin, Hyuk Hur, Kyoung Eun Chang, Incheol Cho, Kieyoung Woo, Byung Seok Moon, Jameyung Kim, Yeonsoo Ahn, Dahee Sim, Sungbong Park, Wook Lee, Kooktae Kim, Chong Kwang Chang, Hansik Yoon, Juha Kim, Sung-In Kim, Hyunchul Kim, Chang-Rok Moon, Jaihyuk Song

Samsung · Samsung
ISSCC
2024

8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1
DOI
Hyo-Jin Park, Joo-Mi Cho, Chan-Ho Lee, Young-Ju Oh, Hyunwoo Jeong, Jun-Hyeok Yang, Jaeseung Lee, Sung-Wan Hong

Sogang University · Samsung
ISSCC
2024

9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm
DOI
Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak

Samsung
ISSCC
2024

9.6 A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm
DOI
Jongmi Lee, Seong-Eun Cho, Jaehoon Lee, Yong Lim, Seunghyun Oh, Jongwoo Lee, Sung-Ung Kwak

Samsung
JSSC
2024

A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces
DOI
Seongcheol Kim, Changmin Sim, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Junseob So, Hwaseok Shin, Seon-Been Lee, Chulwoo Kim

Korea University · Samsung
JSSC
2024

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications
DOI
Hyun-A Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Dong-Hun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Ga-Ram Choi, Jun-Seo Park, Bo-Hyeon Lee, Jinhyeok Baek, Daesik Moon, Joo-Youn Lim, Daihyun Lim, Seung-Jun Bae, Tae-Young Oh

Samsung
JSSC
2024

A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping
DOI
Heejin Yang, Ji-Hwan Seol, Rohit Rothe, Zichen Fan, Qirui Zhang, Hun-Seok Kim, David Blaauw, Dennis Sylvester

University of Michigan · Samsung
JSSC
2024

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm
DOI
Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee

Samsung
JSSC
2024

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1–0 MASH Delta-Sigma Modulator With Digital Noise Coupling
DOI
Dong-Hun Lee, Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Samsung · Korea Advanced Institute of Science and Technology
JSSC
2024

A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links
DOI
Woohyun Kwon, Hyosup Won, Taeho Kim, Sejun Jeon, Soon-Won Kwon, Ha-Il Song, Hanho Choi, Bong-Jin Kim, Huxian Jin, Jun-Gi Jo, Woosang Han, Tai-Young Kim, Gain Kim, Jake Eu, Jinho Park, Hyeon-Min Bae

Samsung · SK hynix · Daegu Gyeongbuk Institute of Science and Technology · Korea Advanced Institute of Science and Technology
JSSC
2024

A 3.8-mW 1.9-mΩ/√Hz Electrical Impedance Tomography IC With High Input Impedance and Loading Effect Calibration for 3-D Early Breast Cancer Detect System
DOI
Soyeon Um, Jaehyuk Lee, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung · Samsung
JSSC
2024

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3
DOI
Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jae-Youn Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko

Samsung
JSSC
2024

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection
DOI
Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo Gyuem Rhew, Jongshin Shin

Samsung
JSSC
2024

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization
DOI
Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Jisu Yook, Jihoon Lee, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sung-Sik Park, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim, Sung Ung Kwak

Samsung
JSSC
2024

A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology
DOI
Jeongkyun Kim, Byungho Yook, Youngo Lee, Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do, Minwoo Kwak, Mijoung Kim, Yunrong Li, Hoyoung Tang, Jaeyoung Kim, Inhak Lee, Dongwook Seo, Sangyeop Baeck

Samsung
JSSC
2024

A Fully Integrated Multi-Phase Voltage Regulator With Flying-Capacitor-Based Inter-Inductor Current Self-Balancing Scheme and Charge-Recycling Gate Driver
DOI
Jeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun-Hyeok Yang, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2024

A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS
DOI
Jaehong Jung, Seunghyun Oh, Joomyoung Kim, Jinhyeon Lee, Wonkang Kim, Euiyoung Park, Seungyong Bae, Seungjin Kim, Jaehoon Lee, Yelim Youn, Yeongcheol Jeong, Sung-Sik Park, Kyungsoo Lee, Yong Lim, Junho Huh, Jongwoo Lee

Massachusetts Institute of Technology · Samsung
JSSC
2024

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces
DOI
Jaekwang Yun, Sangyoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong

Seoul National University · Samsung · Kwangwoon University · Sejong University
JSSC
2024

A Single-Ended Inverter-Based Addition-Only Feed-Forward Equalization Transmitter
DOI
Changjae Moon, Jaeyoung Seo, Myungguk Lee, Iksu Jang, Byungsub Kim

Pohang University of Science and Technology · Samsung · Yonsei University
JSSC
2024

A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces
DOI
Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim

Korea University · Samsung
JSSC
2024

A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving −46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal
DOI
Jongsoo Lee, Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo, Beomyu Park, Jeongkyun Woo, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Hojung Kang, John H. Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Dong-Chan Kim, Dae-Young Yoon, Hongjong Park, Sangsung Lee, Jeongyeol Bae, Huijung Kim, Joonhee Lee, Sangmin Yoo

Samsung
JSSC
2024

MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks
DOI
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-Sun Seo, Mingoo Seok

Columbia University · Arizona State University · Cornell Tech · Samsung · Samsung
JSSC
2024

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces
DOI
Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim

Korea University · Samsung
VLSI
2024

A -96.5 dBm-Sensitivity, 14 dBm Peak Power, Self-Interference Resistant IR-UWB Radar Transceiver Supporting Child Presence Detection and Precision Positioning
DOI
Hyun-Gi Seok, Wan Kim, Sinyoung Kim, Jae-Keun Lee, Chanho Kim, Chanbin Ko, Junseong Park, Wonkang Kim, Jongpil Cho, Seungyoung Bae, Youngsea Cho, Wonjun Jung, Junhyeong Kim, Sumin Kang, Hyeokju Na, Byoungjoong Kang, Honggul Han, Hoon Kang, Minki Ahn, Chiyoung Ahn, Sukjin Jung, Hyukjun Sung, Seunghyun Oh, Jae-Eun Lee, Jongwoo Lee, Joonsuk Kim

Samsung
VLSI
2024

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling
DOI
Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung
VLSI
2024

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET
DOI
Junsang Park, Jinwoo Park, Jaemin Hong, Sunjae Park, Dongsuk Lee, Sungno Lee, Hyochul Shin, Kyunghoon Lee, Byeongwoo Koo, Youngjae Cho, Michael Choi, Jongshin Shin

Samsung
VLSI
2024

A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving −85dBc IMD3 in 5nm FinFET
DOI
Byeongwoo Koo, Sunghan Do, Sangkyu Lee, Sangpil Nam, Heewook Shin, Saemin Im, Hyochul Shin, Sungno Lee, Junsang Park, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin

Samsung
VLSI
2024

A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1 Applications
DOI
Gyuseong Kang, Hyunjin Shin, Sanggyeong Won, Dohui Kim, Kyuseong Kim, Soohoh Seol, Sunkyu Lee, Hangil Lee, Yeonho Jung, Jaechul Shim, Kiseok Suh, Sohee Hwang, Daehyun Jang, Sangyeop Baeck, Sei Seung Yoon

Samsung
VLSI
2024

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces
DOI
Kyunghwan Min, Jahoon Jin, Soo-Min Lee, Sodam Ju, Jisu Yook, Jihoon Lee, Yunji Hong, Sung-Sik Park, Sang-Ho Kim, Jongwoo Lee, Hyungjong Ko

Samsung
VLSI
2024

A 5.8W, 0.00086% THD+N, 118dB PSRR Class-D Audio Amplifier with Passive Output Common-Mode Compensation Technique for Wide Output Power Range
DOI
Inhwan Cho, Moo-Yeol Choi, Jaehyeok Byun, Ji-Hun Lee, Myungjin Lee, Dongsu Kim, Jongwoo Lee

Samsung
VLSI
2024

A 96.4%-Efficiency Single-Duty-Cycled Buck-Boost Converter Achieving 1.9mV Ripple and 2.1mV Mode-Change Fluctuation for Mobile OLED Displays
DOI
Jae-Hyun Kim, Yousung Park, Doyoung Kwon, Dong-Kyu Kim, Sung-Chun Park, Yongjae Lee, Jung-Bong Lee, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
VLSI
2024

A Temporal Noise Reduction via 40% Enhanced Conversion Gain in Dual-Pixel CMOS Image Sensor with Full-Depth Deep-Trench Isolation and Locally Lowered-Stack Technology
DOI
Seunghwan Lee, Jeongjin Cho, Shinyoung Choi, Sung Yoon Min, Eunjung Lee, Minji Jung, Kyoungmok Son, Hyunchaul Jeong, Heetak Han, Sachoun Park, Sanghyuck Moon, Seungki Jung, Junseok Yang, Taesub Jung, Howoo Park, Bumsuk Kim, Kyungho Lee, Jesuk Lee

Samsung
VLSI
2024

An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process
DOI
Hyun-chul Hwang, Min-su Kim, Dae-seong Lee, Yong-geol Kim, Byung-su Kim, Kun-hyuk Kang

Samsung
VLSI
2024

An Intra-Body-Power-Transfer System Energized by an Electromagnetic Energy Harvester for Powering Wearable Sensor Nodes
DOI
Hyungjoo Cho, Dongyoon Lee, Hoyong Sung, Heewon Choee, Ji-Hoon Suh, Injun Choi, Donghee Cho, Sohmyung Ha, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · New York University Abu Dhabi
VLSI
2024

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM
DOI
Kyeongtae Nam, Jaehyuk Kim, Dongil Lee, Kyuchang Kang, Sangyun Kim, Changyoung Lee, Hyunchul Yoon, Donggeon Kim, Bokyeon Won, Jaejoon Song, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang

Samsung
VLSI
2024

Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow
DOI
Seongyon Hong, Wooyoung Jo, Sangjin Kim, Sangyeob Kim, Kyomin Sohn, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung
A-SSCC
2023

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications
DOI
Hyun-A Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Ga-Ram Choi, Jun-Seo Park, Bo-Hyeon Lee, Jinhyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-soo Sohn, Changsik Yoo, Tae-Young Oh

Samsung
A-SSCC
2023

A 1.08ms Ultrafast Scanning Capacitive Touch-Screen Sensor Interface with Charge-Interpolated Common-Mode Compensation and Host-Based Adaptive Median Filtering
DOI
Jonghang Choi, Subin Kim, Yongjun Lee, Sanghyun Heo, Keum-Dong Jung, Young-Ha Hwang, Jun-Eun Park

Sungkyunkwan University · Samsung · Soongsil University
A-SSCC
2023

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1–0 MASH and DNC
DOI
Kent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung
A-SSCC
2023

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3
DOI
Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jae-Youn Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko

Samsung
A-SSCC
2023

A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS
DOI
Dae-Won Rho, Jae-Koo Park, Seung-Jae Yang, Woo-Young Choi

Yonsei University · Samsung
A-SSCC
2023

A Crystal-Less Clock Generator for Low-Power and Low-Cost Sensor Transceivers with 12.9MHz-to-3.3GHz Range, 16.67ppm/°C Inaccuracy from −25°C to 85°C, and 0.25us Settle-Time
DOI
Sangdon Jung, Jehyeok Yu, Minsu Park, Jung-Hoon Chun

Samsung · Sungkyunkwan University
A-SSCC
2023

A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques
DOI
Dong-Hyun Yoon, He Junsen, Kwang-Hyun Baek, Youngdon Choi, Jung-Hwan Choi, Tony Tae-Hyoung Kim

Nanyang Technological University · Chung-Ang University · Samsung
A-SSCC
2023

A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS
DOI
Kyungmin Lee, Jaehong Jung, Gyusik Kim, Joomyoung Kim, Seungjin Kim, Seunghyun Oh, Sung Min Park, Jongwoo Lee

Ewha Womans University · Samsung
A-SSCC
2023

An Area and Power Efficient Fully Nonlinear 10-bit Column Driver with Time-Shared Multi-Gamma-Slope DAC and Time-Interleaved Sampling Buffer for Mobile AMOLEDs
DOI
Seung Hun Choi, Jeongmin Kim, Jaewoong Ahn, Junyeol An, Jiwoong Kim, Ohjo Kwon, Ki-Duk Kim, Hyung-Min Lee

Korea University · Samsung
A-SSCC
2023

Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in NAND Flash Memory
DOI
Bu-il Nam, Jayang Yoon, Kyunghea Lee, Sol Kim, Junhong Park, Chi-Weon Yoon, Eunkyoung Kim

Samsung
CICC
2023

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL
DOI
Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin

Samsung
CICC
2023

A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance
DOI
Junghyun Yoon, MoonHyung Jang, Changuk Lee, Yong Lim, Youngcheol Chae

Yonsei University · Samsung
ESSERC
2023

A 3.8 mW 1.9 m Ω/√Hz Electrical Impedance Tomography Imaging with 28.4 M Ω High Input Impedance and Loading Calibration
DOI
Soyeon Um, Jaehyuk Lee, Hoi-Jun Yoo

Korea Advanced Institute of Science and Technology · Samsung · Samsung
ISSCC
2023

26.1 A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/µs Slew Rate for 8K Displays and Beyond
DOI
Kyungho Ryu, Ji-Yong Jeong, Jung-Pil Lim, Kil-Hoon Lee, Kyongho Kim, Yongil Kwon, Seongjong Yoo, Siwoo Kim, Hyun-Wook Lim, Jae-Youl Lee

Samsung
ISSCC
2023

26.3 A 45.8dB-SNR 120fps 100pF-Load Self-Capacitance Touch-Screen Controller with Enhanced In-Band Common Noise Immunity Using Noise Antenna Reference
DOI
Sanho Byun, Heejin Lee, Tae-Gyun Song, Jinchul Lee, Jongmin Baek, Gyeongmin Ha, Seunghoon Baek, Yeongmin Kim, Wongab Jung, Hyun-Wook Lim, Siwoo Kim, Jae-Youl Lee

Samsung
ISSCC
2023

28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL
DOI
Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jungbum Shin, Yanggyoon Loh, Chang Yong Lee, Junmyung Woo, Hyeseung Yu, Changhyun Bae, Reum Oh, Young-soo Sohn, Changsik Yoo, Jooyoung Lee

Samsung
ISSCC
2023

30.5 A 95.3% 5V-to-32V Wide Range 3-Level Current Mode Boost Converter with Fully State-based Phase Selection Achieving Simultaneous High-Speed $\mathbf{V}_{\text{CF}}$ Balancing and Smooth Transition
DOI
Seung-Ju Lee, Yeon-Woo Jeong, Mun-Jung Cho, Jong-Hun Kim, Hwa-Soo Kim, Jun-Suk Bang, Se-Un Shin

Ulsan National Institute of Science and Technology · Samsung
ISSCC
2023

32.1 A Behind-The-Ear Patch-Type Mental Healthcare Integrated Interface with 275-Fold Input Impedance Boosting and Adaptive Multimodal Compensation Capabilities
DOI
Hyunjoong Kim, Myeongwoo Kim, Kwangmuk Lee, Sanghyeon Cho, Chan Sam Park, Solwoong Song, Dae Sik Keum, Dong Pyo Jang, Jae Joon Kim

Ulsan National Institute of Science and Technology · Samsung · Hanyang University
ISSCC
2023

A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend
DOI
Ji-Hwan SeoI, Heejin Yang, Rohit Rothe, Zichen Fan, Qirui Zhang, Hun-Seok Kim, David Blaauw, Dennis Sylvester

University of Michigan · Samsung
ISSCC
2023

A 0.64μm 4-Photodiode 1.28μm 50Mpixel CMOS Image Sensor with 0.98e- Temporal Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower
DOI
Hyuncheol Kim, Yun Hyeok Kim, Sanghyuck Moon, Hwanwoong Kim, Byeongjun Yoo, Jueun Park, Seyoung Kim, June-Mo Koo, Sewon Seo, Hye Ji Shin, Younghwan Choi, Jinwoo Kim, Kyungil Kim, Jae-Hoon Seo, Seunghyun Lim, Taesub Jung, Howoo Park, Sangil Jung, Juhyun Ko, Kyungho Lee, JungChak Ahn, JoonSeo Yim

Samsung
ISSCC
2023

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection
DOI
Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin

Samsung
ISSCC
2023

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization
DOI
Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim

Samsung
ISSCC
2023

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques
DOI
Kihwan Seong, Donguk Park, Gyeomje Bae, Hyunwoo Lee, Youngseob Suh, Wooseuk Oh, Hyemun Lee, Juyoung Kim, Takgun Lee, Geonhoo Mo, Sukhyun Jung, Dongcheol Choi, Byoung-Joo Yoo, Sanghune Park, Hyo-Gyuem Rhew, Jongshin Shin

Samsung
JSSC
2023

A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution
DOI
Yongtae Lee, Byeonghwa Cho, Changuk Lee, Jongbaeg Kim, Youngcheol Chae

Yonsei University · Samsung
JSSC
2023

A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication
DOI
Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Uijong Song, Chang-Yeon Cho, Giyeong Ko, Hyunseok Hwang, Junseo Lee, Han-Sol Lee, Yong-Il Kwon, Kyungduck Seo, Taeseon Kim, Hyun-Wook Lim, Seongwook Song, Jae-Youl Lee, Sung Ung Kwak

Samsung
JSSC
2023

A 13.56-MHz Wireless Power and Data Transfer System With Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Voltage Regulation
DOI
Minjae Kim, Hyun-Su Lee, Jisan Ahn, Hyung-Min Lee

Korea University · Samsung
JSSC
2023

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features
DOI
Yesin Ryu, Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong Ki Kim, Hyochang Kim, Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyoung-Hwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong, Sunghwan Joo, Dajung Cho, So Young Kim, Minsu Lee, Hyunho Kim, Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn, Sang-Joon Hwang, Jooyoung Lee

Samsung
JSSC
2023

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
DOI
Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, Dae-Hyun Kwon, Chulhee Cho, Sang-Hoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Young Park, Hyoung-Joo Kim, Hoseok Seol, Juhwan Kim, Jungbum Shin, Gil-Young Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chan-Yong Lee, Seungseob Lee, Tae-Hoon Park, Chi-Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-Young Oh, Sang-Joon Hwang, Kyung-Suk Oh, Jung-Hwan Choi, Jooyoung Lee

Samsung
JSSC
2023

A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links
DOI
Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim

Samsung · Pohang University of Science and Technology · Yonsei University
JSSC
2023

A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V pp and T-CMRR of 105 dB in 180-nm CMOS
DOI
Nahmil Koo, Hyojun Kim, Seonghwan Cho

Samsung · Samsung · Korea Aerospace Research Institute · Korea Advanced Institute of Science and Technology
JSSC
2023

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier
DOI
Hyunchul Yoon, Changuk Lee, Taewoong Kim, Yigi Kwon, Youngcheol Chae

Yonsei University · Samsung
JSSC
2023

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
DOI
Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

IBM · IBM · Samsung · Providence Park Hospital
JSSC
2023

A Baseline-Tracking Single-Channel I/Q Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring
DOI
Chan Sam Park, Hyunjoong Kim, Kwangmuk Lee, Dae Sik Keum, Dong Pyo Jang, Jae Joon Kim

Ulsan National Institute of Science and Technology · Samsung · Hanyang University
JSSC
2023

A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os
DOI
Han Wu, Jeong Hoan Park, Rucheng Jiang, Jung-Hwan Choi, Jerald Yoo

National University of Singapore · Samsung
JSSC
2023

A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications
DOI
Gicheol Shin, Eunyoung Lee, Jongmin Lee, Yongmin Lee, Yoonmyung Lee

Sungkyunkwan University · Samsung
JSSC
2023

A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process
DOI
Wan Kim, Hyun-Gi Seok, Geunhaeng Lee, Sinyoung Kim, Jae-Keun Lee, Chanho Kim, Wonkang Kim, Wonjun Jung, Youngsea Cho, Seungyong Bae, Jongpil Cho, Hyuokju Na, Byoungjoong Kang, Honggul Han, Hyeonuk Son, Suhyeon Lee, Dongsu Kim, Ji-Seon Paek, Seunghyun Oh, Jongwoo Lee, Sungung Kwak, Joonsuk Kim

Samsung
JSSC
2023

A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current
DOI
Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · New York University Abu Dhabi · New York University
JSSC
2023

A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC
DOI
Jun-Seok Park, Changsoo Park, Suknam Kwon, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee, James Kim, Hyeong-Seok Kim, YoungJong Lee, Sangkyu Park, MinSeong Kim, SangHyuck Ha, Jihoon Bang, Jinpyo Park, SukHwan Lim, Inyup Kang

Samsung
JSSC
2023

A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM
DOI
Yeonwook Jung, Seongseop Lee, Hyojun Kim, Seonghwan Cho

Korea Advanced Institute of Science and Technology · Samsung · SK hynix · Korea Aerospace Research Institute
JSSC
2023

An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays
DOI
Gyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
JSSC
2023

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s
DOI
Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Kiryong Kim, Byoung Mo Moon, Kyomin Sohn, Seong-Ook Jung

Yonsei University · Samsung
JSSC
2023

An RC Delay-Based Pressure-Sensing System With Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP Monitoring Systems
DOI
Donguk Seo, Minsik Cho, Minhyeok Jeong, Gicheol Shin, Inhee Lee, David Blaauw, Yoonmyung Lee

Sungkyunkwan University · Samsung · University of Pittsburgh · University of Michigan
JSSC
2023

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices
DOI
Sehee Lim, Youngin Goh, Young Kyu Lee, Dong Han Ko, Junghyeon Hwang, Yeongseok Jeong, Hunbeom Shin, Sanghun Jeon, Seong-Ook Jung

Yonsei University · Samsung · Korea Advanced Institute of Science and Technology
JSSC
2023

Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC
DOI
Jae-Gon Lee, Younsik Choi, Hoyeon Jeon, Jong-Jin Lee, Dongsuk Shin

Samsung
JSSC
2023

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference
DOI
Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-Sun Seo, Mingoo Seok

Columbia University · Huawei · Arizona State University · Qualcomm · Samsung · Samsung
VLSI
2023

5G NR RF PA Supply Modulator Supporting 179ns 0.5-to-5.5V Symbol Power Tracking and Envelope Tracking
DOI
Jun-Suk Bang, Dongsu Kim, Younghwan Choo, Ik-Hwan Kim, Seungchan Park, Jeongkwang Lee, Sang-Han Lee, Young-Ho Jung, Jae-Young Ko, Sungyoub Jung, Jaeyeol Han, Woosik Kim, Ji-Seon Paek, Jongwoo Lee

Samsung · Pusan National University
VLSI
2023

A 110dB-TCMRR TDM-based 8-Channel Noncontact ECG Recording IC with Suppression of Motion-Induced Coupling in <0.3s and CMI Cancellation up to 22VPP
DOI
Kyu-Jin Choi, Seungnam Choi, Jae-Yoon Sim

Pohang University of Science and Technology · Samsung
VLSI
2023

A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V
DOI
Gyuseong Kang, Hyunjin Shin, Hyuntaek Jung, Sunkyu Lee, Jaeseung Choi, Sangyeop Baek, Hyunsung Jung, Daeshik Kim, Sohee Hwang, Shinhee Han, Yongsung Ji, Sei Seung Yoon

Samsung
VLSI
2023

A 16-channel Active-Matrix Mini-LED Driver with an USI-B for EMI noise reduction
DOI
Y. Kwon, Y. Kwak, Y. Choi, K. Kim, S. Kim, W. Jang, J. Park, K. Ryu, S. Yoo, H.W. Lim, J. Y. Lee

Samsung
VLSI
2023

A 187dB FoMS 46fJ/Conv. 2nd-order Highpass Δ∑ Capacitance-to-Digital Converter
DOI
Yoontae Jung, Sein Oh, Jimin Koo, Seunga Park, Ji-Hoon Suh, Donghee Cho, Sohmyung Ha, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · New York University Abu Dhabi
VLSI
2023

A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS
DOI
Jaehong Jung, Kyungmin Lee, Gunwoo Kong, Baekmin Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee

Samsung
VLSI
2023

A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package
DOI
Youngmin Jo, Anil Kavala, Tongsung Kim, Byungkwan Chun, Jung-June Park, Taesung Lee, Jungmin Seo, Manjae Yang, Taehyeon Park, Hyunjin Kwon, Cheolhui Lee, Younghoon Son, Junghwan Kwak, Younggyu Lee, Hwan Seok Ku, Daehoon Na, Changyeon Yu, Jonghoon Park, JaeHwan Kim, Hyojin Kwon, Chanho Kim, Moon-Ki Jung, Chanjin Park, Donghyun Seo, Moosung Kim, Seungjae Lee, Jin-Yub Lee, Dongku Kang, Chiweon Yoon, SungHoi Hur

Samsung
VLSI
2023

A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology
DOI
Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck

Samsung
VLSI
2023

A 6.5nW, -73.5dBm Sensitivity, Cryptographic Wake-Up Receiver with a PUF-based OTP and Temperature-Insensitive Code Recovery
DOI
Jaehan Park, Cheonhoo Jeon, Donggyu Minn, Heesung Roh, Jae-Yoon Sim

Pohang University of Science and Technology · Samsung
VLSI
2023

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC
DOI
Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung Mo Moon, Kyomin Sohn, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2023

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications
DOI
Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2023

An Indirect Time-of-Flight CMOS Image Sensor Achieving Sub-ms Motion Lagging and 60fps Depth Image from On-chip ISP
DOI
Jiheon Park, Daeyun Kim, Hoyong Lee, Seung-Chul Shin, Myoungoh Ki, Bumsik Chung, Myunghan Bae, Myeonggyun Kye, Jonghan Ahn, Inho Song, Sunhwa Lee, Jaeil An, Il-Pyeong Hwang, Taemin An, Young-Gu Jin, Youngchan Kim, Youngsun Oh, Juhyun Ko, Haechang Lee, JoonSeo Yim

Samsung
A-SSCC
2022

110.1dB DR 4-ch Audio ADCs and 98dB DR 2-ch Voice-Triggering ADCs in Reconfigurable Architecture with Enhanced Off-Transistor-Based Bias Noise Filter
DOI
Moo-Yeol Choi, Inhwan Cho, Myungjin Lee, Seunghyun Oh, Jongwoo Lee

Samsung
A-SSCC
2022

A 0.55mm2 16.9mW Fully Integrated 0-to-200MHz System BW Wireless Direct Sampling Receiver in 14nm FinFET
DOI
Ilhoon Jang, Barosaim Sung, Jaehoon Lee, Soonwoo Choi, Byoungjoong Kang, Suseob Ahn, Kyungmin Lee, Taejin Jang, Kwangmin Lim, Anna Yu, Yong Lim, Seunghyun Oh, Jongwoo Lee

Samsung
A-SSCC
2022

A 0.95pJ/b 5.12Gb/s/pin Charge-Recycling IOs with 47% Energy Reduction for Big Data Applications
DOI
Han Wu, Jeong Hoan Park, Miaolin Zhang, Longyang Lin, Rucheng Jiang, Jung-Hwan Choi, Jerald Yoo

National University of Singapore · Samsung · Southern University of Science and Technology
A-SSCC
2022

A 103.8-dB DR 25ps-to-35ns Resolution Time-to-Digital Converter with Dynamic Ring Oscillator for LiDAR Applications
DOI
Taewoong Kim, Sanghoon Lee, Youngcheol Chae

Yonsei University · Samsung
A-SSCC
2022

A 11.4-Gbps/lane MIPI 32-bit C-PHY and D-PHY combo transmitter with 3-tap FFE
DOI
Junhan Bae, Myeongkyu Song, Bongkyu Kim, Junkyu Lee, Woosung Park, Jung-Hoon Chun

Sungkyunkwan University · Samsung
A-SSCC
2022

A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-less Sub-sampling CDR with Beat Detection FLL in 28nm CMOS
DOI
Woosung Park, Jahoon Jin, Minsu Park, Sangdon Jung, Jung-Hoon Chun

Samsung · Sungkyunkwan University
A-SSCC
2022

A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation
DOI
Ju Eon Kim, Dong-Hyun Yoon, Junyoung Song, Kwang-Hyun Baek, Jung-Hwan Choi, Tony Tae-Hyoung Kim

Nanyang Technological University · Samsung · Incheon National University · Chung-Ang University
A-SSCC
2022

A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS
DOI
Daesik Moon, Sangwoo Lee, Taewoong Kim, Woo-Young Choi, Youngcheol Chae

Yonsei University · Samsung · Bosch
A-SSCC
2022

A Digital Temperature Sensor Based on 10b SAR ADC for Non-linear Temperature Dependency Compensation in 3D NAND Flash Memory
DOI
Kyoung-Jun Roh, Min-Ki Jeon, Jaewoo Park, Myoungbo Kwak, Chi-Weon Yoon, Youngdon Choi, Jung-Hwan Choi

Samsung
A-SSCC
2022

A Hybrid Temperature Compensation method combined with Digital and Analog Temperature Compensation Techniques for 3D-NAND Flash Memories
DOI
Dojeon Lee, Junhong Park, Philkyu Kang, Sungmin Jo, Seheon Baek, Chi-Weon Yoon, Dongku Kang

Samsung
A-SSCC
2022

A Single-Ended Duobinary-PAM4(PAM7) Transmitter with a 2-Tap Feed-Forward Equalizer
DOI
Jaenam Kim, Sanghyeon Park, Jaewoo Park, Junhan Bae, Jung-Hoon Chun

Samsung · Sungkyunkwan University
A-SSCC
2022

A Synchronous-Sampling Impedance-Readout IC with Baseline-Cancellation-Based Two-Step Conversion for Fast Neural Electrical Impedance Tomography
DOI
Ji-Hoon Suh, Haidam Choi, Yoontae Jung, Sein Oh, Hyungjoo Cho, Nahmil Koo, Seong Joong Kim, Chisung Bae, Sohmyung Ha, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · Samsung · New York University Abu Dhabi
A-SSCC
2022

High-speed Serial Link Trend and Technical Challenge
DOI
Hyungjong Ko

Samsung
CICC
2022

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology
DOI
Taejoong Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, Woojin Rim, Sanghoon Baek, Sangyeop Baeck, Jonghoon Jung

Samsung
CICC
2022

A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks
DOI
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok

Columbia University · Arizona State University · Samsung · Samsung
CICC
2022

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process
DOI
Joohwan Kim, Junyoung Park, Jindo Byun, Changkyu Seol, Chang Soo Yoon, EunSeok Shin, Hyunyoon Cho, Youngdo Um, Sucheol Lee, Hyungmin Jin, Kwangseob Shin, Hyunsub Norbert Rie, Minsu Jung, Jin-Hee Park, Go-Eun Cha, Minjae Lee, YoungMin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, Hyejeong So, Sungduk Kim, Wansoo Park, Tae young Kim, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Sang-Hyun Lee

Samsung
CICC
2022

A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor
DOI
Woojoong Jung, Minsu Kim, Hyunjun Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee

Korea University · Samsung
CICC
2022

A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation
DOI
Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je

Korea Advanced Institute of Science and Technology · Samsung · New York University Abu Dhabi
ESSERC
2022

A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec
DOI
Jaehyun Ko, Iksu Jang, Chanho Kim, Jihoon Park, Changjae Moon, Sooeun Lee, Byungsub Kim

Pohang University of Science and Technology · Samsung
ESSERC
2022

A Pipeline ADC with Negative C-assisted SC Amplifier Canceling Gain Error and Nonlinearity
DOI
Woojin Jang, Gyeong-Gu Kang, Yong Lim, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
ESSERC
2022

SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution
DOI
Sumin Lee, Ki-Beom Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-Ook Jung

Yonsei University · Samsung
ISSCC
2022

2-Tx Digital Envelope-Tracking Supply Modulator Achieving 200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF Power Amplifiers
DOI
Jun-Suk Bang, Dongsu Kim, Jeongkwang Lee, Sungyoub Jung, Younghwan Choo, Seungchan Park, Young-Ho Jung, Jae-Young Ko, Takahiro Nomiyama, Jongbeom Baek, Jaeyeol Han, Sang-Han Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho

Samsung
ISSCC
2022

A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS
DOI
Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin

Samsung
ISSCC
2022

A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication
DOI
Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Shin-Wuk Kang, Uijong Song, Chang-Yeon Cho, Junseo Lee, Kyungduck Seo, Seongwook Song, Sung Ung Kwak

Samsung
ISSCC
2022

A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns
DOI
Jeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Younghwan Choo, Ji-Seon Paek, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
ISSCC
2022

A 1/1.57-inch 50Mpixel CMOS Image Sensor With 1.0μm All-Directional Dual Pixel by 0.5μm-Pitch Full-Depth Deep-Trench Isolation Technology
DOI
Taesub Jung, Masato Fujita, Jeongjin Cho, Kyungduck Lee, Doosik Seol, Sungmin An, Chanhee Lee, Youjin Jeong, Minji Jung, Sachoun Park, Seungki Baek, Seungki Jung, Seunghwan Lee, Jungbin Yun, Eun Sub Shim, Heetak Han, Eunkyung Park, Haesick Sul, Sehyeon Kang, Kyungho Lee, JungChak Ahn, Duckhyun Chang

Samsung
ISSCC
2022

A 10b Source-Driver IC with LSB-Stacked LV-to-HV-Amplify DAC Achieving 2688μm2/channel and 4.8mV DVO for Mobile OLED Displays
DOI
Gyu-Wan Lim, Gyeong-Gu Kang, Hyunggun Ma, Moonjae Jeong, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
ISSCC
2022

A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW
DOI
Ashutosh Verma, Venu Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang Ivan Lu, Sang Won Son, Thomas B. Cho

Samsung · Samsung
ISSCC
2022

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus
DOI
Daewoong Lee, Hye-Jung Kwon, Daehyun Kwon, Jaehyeok Baek, Chulhee Cho, Sanghoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Young Park, HyoungJoo Kim, Hoseok Seol, Juhwan Kim, Junabum Shin, Kil-Youna Kang, Yona-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chanyong Lee, Seungseob Lee, TaeHoon Park, ChiSung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-Young Oh, SangJoon Hwang, Kyung Suk Oh, JungHwan Choi, Jooyoung Lee

Samsung
ISSCC
2022

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
DOI
Dae-Hyun Kim, Byungkyu Song, Hyun-a Ahn, Woongjoon Ko, Sunggeun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jongmin Bang, Bokgue Park, Janghoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Won-Il Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee

Samsung
ISSCC
2022

A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface
DOI
Moosung Kim, Sung Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee, Yeong Seon Kim, Daehoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyunjun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Jisang Lee, Jin Young Chun, Joonsuc Jang, Younghwi Yang, Seung Hyun Moon, Myunghoon Choi, Wontae Kim, Jungsoo Kim, Seokmin Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sunghoon Kim, Chiweon Yoon, Dongku Kang, Jin-Yub Lee, Jaihyuk Song

Samsung
ISSCC
2022

A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces
DOI
Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim

Pohang University of Science and Technology · Samsung
ISSCC
2022

A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital Converters
DOI
Henry Hinton, Houk Jang, Wenxuan Wu, Min-Hyun Lee, Minsu Seol, Hyeon-Jin Shin, Seongjun Park, Donhee Ham

Harvard University · Samsung · Samsung
ISSCC
2022

A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS
DOI
Jaehong Jung, Seungjin Kim, Wonkang Kim, Jaeyeol Han, Euiyoung Park, Seongwook Hwang, Seunghyun Oh, Sangwook Han, Kyungsoo Lee, Junho Huh, Jongwoo Lee

Samsung
ISSCC
2022

A 64Mpixel CMOS Image Sensor with 0.56μm Unit Pixels Separated by Front Deep-Trench Isolation
DOI
Sungbong Park, ChangKyu Lee, Sangcheon Park, Haeyong Park, Taeheon Lee, Dami Park, Minsung Heo, Inyong Park, Hyunyoung Yeo, Youna Lee, Juhee Lee, Beomsuk Lee, Dong-Chul Lee, Jinyoung Kim, Bokwon Kim, Jinsun Pyo, Shili Quan, Sungyong You, Inho Ro, Sungsoo Choi, Sung-In Kim, In-Sung Joe, Jongeun Park, Chang-Hyo Koo, Jae-Ho Kim, Chong Kwang Chang, Taehee Kim, JinGyun Kim, Jamie Lee, Hyunchul Kim, Chang-rok Moon, Hyoung-Sub Kim

Samsung
ISSCC
2022

A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC
DOI
Jun-Seok Park, Changsoo Park, Suknam Kwon, Hyeong-Seok Kim, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee, James Kim, YoungJong Lee, Sangkyu Park, Jun-Woo Jang, SangHyuck Ha, MinSeong Kim, Jihoon Bang, Suk Hwan Lim, Inyup Kang

Samsung · Samsung
ISSCC
2022

A Reconfigurable Series-Parallel Charger for Dual-Battery Applications with 89W 97.7% Efficiency in Direct Charging Mode
DOI
Sungwoo Lee, Taejin Jeong, Yonghwan Cho, Jeongdu Yoo, Sungkyu Cho, Minkyu Kwon, Daewoong Cho, Sang Hee Kang, Jung Wook Heo, Hyoung-Seok Oh, Sung Ung Kwak

Samsung
ISSCC
2022

A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration
DOI
Jaehong Jung, Seunghyun Oh, Joomyoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seungyong Bae, Wonkang Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, Thomas Byunghak Cho

Samsung
ISSCC
2022

A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET
DOI
Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sungjun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Byunghak Cho, Inyup Kang

Samsung
ISSCC
2022

A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter
DOI
Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho

Samsung · SK hynix · Korea Aerospace Research Institute · Korea Advanced Institute of Science and Technology
ISSCC
2022

Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application
DOI
Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin

Samsung
ISSCC
2022

Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC
DOI
Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim

Samsung
ISSCC
2022

The Art of Scaling: Distributed and Connected to Sustain the Golden Age of Computation
DOI
Inyup Kang

Samsung
JSSC
2022

2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory
DOI
Min-Woong Seo, Myunglae Chu, Hyun-Yong Jung, Suksan Kim, Jiyoun Song, Daehee Bae, Sanggwon Lee, Junan Lee, Sung-Yong Kim, Jongyeon Lee, Minkyung Kim, Gwi-Deok Lee, Heesung Shim, Changyong Um, Changhwa Kim, In-Gyu Baek, Doowon Kwon, Hongki Kim, Hyuksoon Choi, Jonghyun Go, Jungchak Ahn, Jae-Kyu Lee, Chang-Rok Moon, Kyupil Lee, Hyoung-Sub Kim

Samsung
JSSC
2022

A 0.5–1 V, −68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS
DOI
Jun-Hwan Jang, Hui-Dong Gwon, Tae-Hwang Kong, Jun-Hyeok Yang, Byong-Deok Choi

Hanyang University · Samsung
JSSC
2022

A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From −40 °C to 85 °C
DOI
Woojun Choi, Jan Angevare, Injun Park, Kofi A. A. Makinwa, Youngcheol Chae

ETH Zurich · Delft University of Technology · Samsung · Yonsei University
JSSC
2022

A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit
DOI
Taejoong Song, Hoonki Kim, Woojin Rim, Hakchul Jung, Changnam Park, Inhak Lee, Sanghoon Baek, Jonghoon Jung

Samsung
JSSC
2022

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC
DOI
Ji-Young Kim, Jongsoo Lee, Kiryong Kim, Sunghwan Joo, Byoung Mo Moon, Kyomin Sohn, Seong-Ook Jung

Yonsei University · Samsung
JSSC
2022

A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control
DOI
Venumadhav Bhagavatula, Fan Zhang, Chechun Kuo, Anirban Sarkar, Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Dae-Young Yoon, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho

Samsung · Samsung
JSSC
2022

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks
DOI
Chengshuo Yu, Taegeun Yoo, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim

Agency for Science, Technology and Research · Nanyang Technological University · Institute of Microelectronics · Samsung · University of California, Santa Barbara
JSSC
2022

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique
DOI
Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu

Korea Advanced Institute of Science and Technology · Samsung · Gachon University
JSSC
2022

A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques
DOI
Jeong-Hyun Cho, Dong-Kyu Kim, Hong-Hyun Bae, Yong-Jin Lee, Seok-Tae Koh, Younghwan Choo, Ji-Seon Paek, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung · SK hynix
JSSC
2022

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
DOI
Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi

Korea Advanced Institute of Science and Technology · Samsung · Ulsan National Institute of Science and Technology
JSSC
2022

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET
DOI
Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sungjun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee

Samsung
JSSC
2022

A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces
DOI
Yoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Injun Choi, Jimin Koo, Mi Kyung Kim, Hyunjoo Jenny Lee, Sohmyung Ha, Minkyu Je

Korea Advanced Institute of Science and Technology · New York University Abu Dhabi · New York University · Chungbuk National University · Samsung
JSSC
2022

An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires
DOI
Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun

Samsung · Sungkyunkwan University
JSSC
2022

An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation
DOI
Geunhaeng Lee, Junyoung Jang, Ji-Hoon Kim, Tae Wook Kim

Yonsei University · Samsung · Ewha Womans University
JSSC
2022

Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End
DOI
Ji-Seon Paek, Dongsu Kim, Jae-Yeol Han, Younghwan Choo, Jun-Suk Bang, Seungchan Park, Jongbeom Baek, Takahiro Nomiyama, Ik-Hwan Kim, Jongwoo Lee

Samsung
JSSC
2022

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling
DOI
Keonhee Cho, Heekyung Choi, In Jun Jung, Jisang Oh, Tae Woo Oh, Kiryong Kim, Giseok Kim, Taemin Choi, Changsu Sim, Taejoong Song, Seong-Ook Jung

Yonsei University · Samsung
JSSC
2022

Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs
DOI
Hyun-Chul Park, Seokhyeon Kim, Jooseok Lee, Junho Jung, Seungjae Baek, Taewan Kim, Daehyun Kang, Donggyu Minn, Sung-Gi Yang

Samsung
VLSI
2022

0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link
DOI
Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong

Seoul National University · SK hynix · Samsung
VLSI
2022

4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits
DOI
Inhak Lee, Dongwook Seo, Yunrong Li, Mijoung Kim, Sangyeop Baeck

Samsung
VLSI
2022

A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET
DOI
Jaehoon Lee, Yong Lim, Jongmi Lee, Taejin Jang, Kwonwoo Kang, Jongpil Cho, Seunghyun Oh, Jongwoo Lee

Samsung
VLSI
2022

A 0.7 mm2 Power Management Unit for Implantable Electroceutical Device with a 91.4 % Peak Efficiency Buck-based Hybrid Step-up and -down MISIMO Converter
DOI
Yeunhee Huh, Chisung Bae, Hankyu Lee, Sang Joon Kim

Samsung
VLSI
2022

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET
DOI
Kyoung-Jun Moon, Dong-Ryeol Oh, Young-Hyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyo-Chul Shin, Young-Jae Cho, Michael Choi, Jong-Shin Shin

Samsung
VLSI
2022

A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET
DOI
Byeongwoo Koo, Sunghan Do, Sangpil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin

Samsung
VLSI
2022

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications
DOI
Keonhee Cho, Giseok Kim, Jisang Oh, Kiryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2022

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features
DOI
Yesin Ryu, Young-Cheon Kwon, Jae Hoon Lee, Sung-Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han-Won Cho, Jae San Kim, Jungyu Lee, Haesuk Lee, Seung Ho Song, Je Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae-Seung Jeong, Sukhan Lee, Kyoung-Hwan Lim, Tae-Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung-Kyu Lee, Sunghye Cho, Sung-Rae Kim, Ji-Min Choi, Hyoung Min Kim, Soo Young Kim, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee

Samsung
VLSI
2022

A 25.78125Gbps Bi-directional Transceiver with Framed-Pulsewidth Modulation (FPWM) for Extended Reach Optical Links in 28nm CMOS
DOI
Woohyun Kwon, Hyosup Won, Taeho Kim, Ha-Il Song, Hanho Choi, Sejun Jeon, Soon-Won Kwon, Huxian Jin, Jun-Gi Jo, Tai-Young Kim, Jake Eu, Jinho Park, Hyeon-Min Bae, Bongjin Kim

Korea Advanced Institute of Science and Technology · Samsung
VLSI
2022

A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications
DOI
Seki Kim, Hyongmin Lee, Yongjin Lee, Dongha Lee, Byeongbae Lee, Jahoon Jin, Susie Kim, Miri Noh, Kwonwoo Kang, Sangho Kim, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee

Samsung
VLSI
2022

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application
DOI
Hyunsub Norbert Rie, Chang Soo Yoon, Jindo Byun, Sucheol Lee, Garam Kim, Joohwan Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, Minsu Jung, Go-Eun Cha, Minjae Lee, YoungMin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, EunSeok Shin, Hyuk-Jun Kwon, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko

Samsung
VLSI
2022

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier
DOI
Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae

Yonsei University · Samsung
VLSI
2022

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links
DOI
Timothy Dickson, Zeynep Deniz, Martin Cochet, Marcel Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brandli, Troy Beukema, Christian Baks, Jonathan Proesel, John Bulzacchelli, Michael Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

IBM · IBM · Samsung
VLSI
2022

A Fully-Integrated 0.9W/mm2 79.1%-Efficiency 200MHz Multi-Phase Buck Converter with Flying-Capacitor-Based Inter-Inductor Current Balancing Technique
DOI
Jeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun-Hyeok Yang, Hyun-Sik Kim

Korea Advanced Institute of Science and Technology · Samsung
VLSI
2022

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM
DOI
Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Kiryong Kim, Byoung Mo Moon, Kyomin Sohn, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2022

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS
DOI
A. Serdar Yonar, Pier Andrea Francese, Matthias Brandli, Marcel Kossel, Thomas Morf, Jonathan E. Proesel, Sergey Rylov, Herschel Ainspan, Martin Cochet, Zeynep Deniz, Timothy Dickson, Troy Beukema, Christian Baks, Michael Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin

ETH Zurich · IBM · IBM · Samsung
VLSI
2022

An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application
DOI
Kyunghoon Lee, Jinwoo Park, Younghyo Park, Byeongwoo Koo, Sunghan Do, Woongtaek Lim, Sungno Lee, Hyochul Shin, Eunhye Oh, Youngjae Cho, Michael Choi, Jongshin Shin

Samsung
VLSI
2022

Fully Integrated 2x2 MIMO Real Simultaneous Dual Band WiFi CMOS Power Amplifiers With a Single Inductor Multiple Output Supply Modulation Technique
DOI
Ji-Seon Paek, Jeong-Kwang Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee

Samsung
VLSI
2022

High Efficiency 29-/38-GHz Hybrid Transceiver Front-Ends Utilizing Si CMOS and GaAs HEMT for 5G NR Millimeter-Wave Mobile Applications
DOI
Youngmin Kim, Hongjong Park, Iljin Lee, Joonhoi Hur, Sangmin Yoo

Samsung