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ISSCC · 2022–2026 LIVE

Seoul National University

対象論文Papers 15 · 筆頭著者first author 12 · 著者按分fractional 10.50 · 韓国Korea #2 · 世界World #19

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Jaehyouk Choi ORCID5
2Woo-Seok Choi ORCID3
3Deog-Kyoon Jeong ORCID2
3Dongsuk Jeon ORCID2
3Ha-Jung Park ORCID2
3Hangi Park ORCID2
3Jerald Yoo ORCID2
3Jung-Hun Park ORCID2
3Kahyun Kim ORCID2
3Munjae Chae ORCID2
3Seheon Jang ORCID2
3Sungjin Park ORCID2
3Yuhwan Shin ORCID2
14Chanwoong Hwang ORCID1
14Chanwoong Hwanq1
14Daehoon Na ORCID1
14Hoyeon Cho1
14Hyeong-Seok Choi1
14Hyeonseok Lee1
14Hyojun Kim ORCID1
14Jaeho Kim ORCID1
14Jaekwang Yun ORCID1
14Jeongbeom Seo1
14Jeongeun Song ORCID1
14Jeongwoo Park ORCID1
14Jia Park ORCID1
14Jihee Kim ORCID1
14Jooeun Bang ORCID1
14Junseok Lee ORCID1
14Juyeop Kim ORCID1
14Kwang-Hoon Lee1
14Myeongho Han ORCID1
14Sanghee Lee1
14Sangsu Jeong ORCID1
14Sangyoon Lee ORCID1
14Suhwan Kim1
14Sunwoo Lee ORCID1
14Woosong Jung ORCID1
14Yongwoo Jo ORCID1
14Yoona Lee1
14Yoonho Song1
14Yoonseo Cho ORCID1

対象論文Papers

  1. ISSCC
    2026
    8.8 A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS
    DOI
    Kahyun Kim, Yoona Lee, Daehoon Na, Ha-Jung Park, Jeongeun Song, Woo-Seok Choi
    Seoul National University
  2. ISSCC
    2026
    A 16.4nJ/Class Patient-Independent Prototype-Based Spatio-Temporal CNN Processor with Forward-Inference-Based Adaptation for Robust and Low-Latency Seizure Detection
    DOI
    Yang Wang, Longyang Lin, Jerald Yoo, Jiamin Li
    Southern University of Science and Technology · Seoul National University
  3. ISSCC
    2026
    A Radiation-Hardened Self-Healing CMOS Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications
    DOI
    Quan Cheng, Zhengke Yang, Haoyuan Li, Qiufeng Li, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jerald Yoo, Masanori Hashimoto, Longyang Lin
    Southern University of Science and Technology · 京都大学Kyoto University · Seoul National University
  4. ISSCC
    2025
    22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces
    DOI
    Kahyun Kim, Jung-Hun Park, Ha-Jung Park, Jia Park, Jihee Kim, Woo-Seok Choi
    Seoul National University · University of California, Berkeley
  5. ISSCC
    2025
    22.2: An $850\mu \mathrm{W}$ 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces
    DOI
    Jeongbeom Seo, Yoonseo Cho, Yuhwan Shin, Jaehyouk Choi
    Seoul National University
  6. ISSCC
    2025
    22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces
    DOI
    Boram Kim, Hankyu Chi, Hyeongjun Ko, Sangyeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jinyoup Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
    SK hynix · Seoul National University
  7. ISSCC
    2025
    34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration
    DOI
    Munjae Chae, Seheon Jang, Chanwoong Hwanq, Hangi Park, Jaehyouk Choi
    Seoul National University
  8. ISSCC
    2025
    8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time
    DOI
    Jaeho Kim, Myeongho Han, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
    Seoul National University · Kyung Hee University
  9. ISSCC
    2025
    A 28nm 18. $1 \mu \mathrm{J}$ /Acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assisted Computing
    DOI
    Sangsu Jeong, Sungjin Park, Mingoo Seok, Dongsuk Jeon
    Seoul National University · Columbia University
  10. ISSCC
    2024
    10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm
    DOI
    Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology
  11. ISSCC
    2024
    10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
    DOI
    Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology
  12. ISSCC
    2023
    22.8 A0.81 mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS
    DOI
    Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Dongsuk Jeon
    Seoul National University
  13. ISSCC
    2023
    A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS
    DOI
    Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong
    Seoul National University
  14. ISSCC
    2022
    A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration
    DOI
    Hyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog-Kyoon Jeong
    Seoul National University · University of California, Berkeley · Columbia University
  15. ISSCC
    2022
    A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
    DOI
    Sangyoon Lee, Jaekwang Yun, Suhwan Kim
    Seoul National University