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大学University · 韓国Korea · 2022–2026 LIVE

Seoul National University

韓国Korea 2位 (65.5 pt) · 世界World 25位 (0 pt) · 対象論文Papers 94

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0510152025302022 ISSCC: 22022 VLSI: 22022 JSSC: 62022 A-SSCC: 32022 ESSERC: 31620222023 ISSCC: 22023 JSSC: 42023 CICC: 12023 A-SSCC: 12023 ESSERC: 21020232024 ISSCC: 22024 VLSI: 12024 JSSC: 32024 CICC: 42024 A-SSCC: 52024 ESSERC: 31820242025 ISSCC: 62025 JSSC: 102025 CICC: 62025 A-SSCC: 42025 ESSERC: 22820252026 ISSCC: 32026 VLSI: 62026 JSSC: 92026 CICC: 4222026
ISSCCVLSIJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC22263
VLSI2–1–6
JSSC643109
CICC–1464
A-SSCC3154–
ESSERC3232–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1151210.50韓国Korea #2 · 世界World #19
VLSI Tier 1966.27韓国Korea #5 · 世界World #24
JSSC Tier 1321314.38韓国Korea #4 · 世界World #19
CICC Tier 2151111.04韓国Korea #2 · 世界World #13
A-SSCC Tier 21345.11韓国Korea #3 · 世界World #11
ESSERC Tier 21087.28韓国Korea #2 · 世界World #13

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A 28nm 34mW Zero Knowledge Proof Processor with Reconfigurable Modular Multiplier Array and Memory-based Successive Excess Reduction
    DOI
    Sangouk Jeon, Sungjin Park, Beomseok Kim, Juyoung Oh, Dongsuk Jeon
    Seoul National University
  2. CICC
    2026
    A Comprehensive Power-Supply-Induced Jitter Mitigation Scheme for HBM Interfaces Using a Strobe-Triggered Digital LDO and Local Replica Regulators Achieving 10.7mV Voltage Droop and 1.4ns Settling Time
    DOI
    Myeongho Han, Jaeho Kim, Hyunjun Song, Jaehyouk Choi
    Seoul National University
  3. CICC
    2026
    A Dynamic-Active Static-Sleep 18T Flip-Flop Supporting Retentive Clock Gating in 28nm CMOS
    DOI
    Dongkwon Lee, Donghyun Kim, Dongsuk Jeon
    Seoul National University
  4. CICC
    2026
    ROM-LTE: A 28nm 16.1TOPS/W ROM-Based LUT Tensor Engine with Complementary ROM and Switching-Suppressed Latch-Based PE for Fine-Tuning-Free ML Inference
    DOI
    Sangsu Jeong, Jeongkyu Park, Dongsuk Jeon
    Seoul National University
  5. ISSCC
    2026
    8.8 A 0.292pJ/b 56Gb/s/wire Capacitively Driven Simultaneous Bidirectional Transceiver with PVT/Mismatch Tracking for XSR and D2D Interfaces in 28nm CMOS
    DOI
    Kahyun Kim, Yoona Lee, Daehoon Na, Ha-Jung Park, Jeongeun Song, Woo-Seok Choi
    Seoul National University
  6. ISSCC
    2026
    A 16.4nJ/Class Patient-Independent Prototype-Based Spatio-Temporal CNN Processor with Forward-Inference-Based Adaptation for Robust and Low-Latency Seizure Detection
    DOI
    Yang Wang, Longyang Lin, Jerald Yoo, Jiamin Li
    Southern University of Science and Technology · Seoul National University
  7. ISSCC
    2026
    A Radiation-Hardened Self-Healing CMOS Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications
    DOI
    Quan Cheng, Zhengke Yang, Haoyuan Li, Qiufeng Li, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jerald Yoo, Masanori Hashimoto, Longyang Lin
    Southern University of Science and Technology · 京都大学Kyoto University · Seoul National University
  8. JSSC
    2026
    A 136.6-dB-DR 174.3-dB-FoM S Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop
    DOI
    Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Yeonjae Shin, Jeongyoon Wie, Seungyeob Baik, Hongki Kang, Minyoung Song, Jong-Hyeok Yoon, Junghyup Lee
    Georgia Institute of Technology · Samsung · Daegu Gyeongbuk Institute of Science and Technology · Korea Institute of Nuclear Safety · Seoul National University
  9. JSSC
    2026
    A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces
    DOI
    Kahyun Kim, Daehoon Na, Jeongeun Song, Hajung Park, Jin-Seok Heo, Hyunjun Park, Jihee Kim, Hanseok Kim, Hyeri Roh, Jung-Hun Park, Woo-Seok Choi
    Seoul National University · Cadence
  10. JSSC
    2026
    A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces
    DOI
    Jaeho Kim, Myeongho Han, Hyunjun Song, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
    Seoul National University · Kyung Hee University
  11. JSSC
    2026
    A Hybrid Bipolar-Output Isolated Gate Driver Power Supply With Primary-Side Regulation and Switched-Capacitor for SiC Power Devices
    DOI
    Joo-Mi Cho, Jeong-Hun Kim, Yong-Chan Lee, Sung-Wan Hong
    Sogang University · Seoul National University
  12. JSSC
    2026
    A Low-Jitter Fractional- N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique
    DOI
    Yuhwan Shin, Juyeop Kim, Junseok Lee, Yongwoo Jo, Jaehyouk Choi
    Korea Advanced Institute of Science and Technology · Samsung · Samsung · Seoul National University
  13. JSSC
    2026
    A Real-Time Deep Reinforcement Learning Processor for Mapless Autonomous Navigation With Unified Actor-Critic Network and Inference-on-Request Scheduling
    DOI
    Juyoung Oh, Jie-Xin Liu, Yi-Chen Teng, Hsueh-Cheng Wang, Dongsuk Jeon
    Seoul National University · National Yang Ming Chiao Tung University
  14. JSSC
    2026
    A Reference-Less All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line in 28-nm CMOS
    DOI
    Minyoung Kang, Sunghoon Kim, Youngmin Park, Sangsu Jeong, Dongsuk Jeon
    Seoul National University
  15. JSSC
    2026
    AdaPIM: A CIM-Based General-Purpose Vision Accelerator With Adaptive Inter-Macro Parallelism and Multi-Level Feature Reuse
    DOI
    Jin Wang, Moxiao Lou, Zhengke Yang, Zhixiong Li, Jiamin Li, Yida Li, Jerald Yoo, Longyang Lin
    Southern University of Science and Technology · Seoul National University
  16. JSSC
    2026
    Falcon: Event-Driven Hybrid Object Tracking SoC With Bit-Column-Similarity-Based MRAM PIM and Heterogeneous Read-Only-Once Attention Flow
    DOI
    Wenao Xie, Haoyang Sang, Zhamaliddin Kalzhan, Jingu Lee, Jerald Yoo, Kangho Lee, Hoi-Jun Yoo
    Korea Advanced Institute of Science and Technology · University of Macau · Seoul National University · Samsung
  17. VLSI
    2026
    A 12 V-to-1V Scalable 2N-Phase Buck Converter Using 0V-Stress Balancer with Shortest $I_{\mathrm{L}}$ Balancing Path for Parallel IC Expansion in xPU Systems
    DOI
    Young-Jun Jeon, Chan-Ho Lee, Jong-Woo Jang, Sung-Wan Hong
    Sogang University · Samsung · Seoul National University
  18. VLSI
    2026
    A 16.8-33.6 Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance Under Deep SSC
    DOI
    Jongwha Kim, Yongwoo Jo, Seongyun Min, Juntak Chun, Yuhwan Shin, Hyunjun Song, Seohyeon Kwak, Kwanseo Park, Jaehyouk Choi
    Seoul National University · Samsung · Yonsei University
  19. VLSI
    2026
    A 28nm 2GS/s Remote-Sensing On-Chip Oscilloscope Using Charge-Redistributing Voltage Transfer and Time-Domain Stochastic ADC with 1.6mV Resolution
    DOI
    Minyoung Kang, Dongkwon Lee, Sangsu Jeong, Kwanghyun Shin, Dongsuk Jeon
    Seoul National University
  20. VLSI
    2026
    A Scalable Distributed Digital LDO Achieving Fast and Accurate Current Balancing
    DOI
    Sang-Yun Nam, Won-Gyu Kim, Jaeseung Lee, Jun-Hyeok Yang, Sung-Wan Hong
    Sogang University · Samsung · Seoul National University
  21. VLSI
    2026
    A Versatile On-Chip Jitter Measurement Circuit with Dynamic Quantizer-Resolution Adaptation for Arbitrary Clocks Across 1–8GHz and 20–130ps pp Jitter
    DOI
    Junseok Lee, Chanwoong Hwang, Jeongbeom Seo, Jaehyouk Choi
    Seoul National University
  22. VLSI
    2026
    Silicon-Oracle (Soracle): A Multi-Modal Autoregressive Model Accelerator for Context-Aware Assistance on Mobile Platform
    DOI
    Wenao Xie, Zhongqi Li, Jiaer Chen, Jerald Yoo, Hoi-Jun Yoo
    Korea Advanced Institute of Science and Technology · Seoul National University
  23. A-SSCC
    2025
    A 12-Channel Multi-Electrode Temporal Interference Stimulation (Multi-TIS) Driver IC with High-Voltage Amplifier and Mismatch Calibration Technique
    DOI
    Hye-Seon Choi, So-Hyun Lee, Myeong-Cheol Hyun, Jae-Ha Lee, Ji-Sun Lee, Myeong-Jun Kim, Kyunghyun Jo, Seongjun Park, Jong-Seok Kim
    Hanyang University · Korea Advanced Institute of Science and Technology · Seoul National University
  24. A-SSCC
    2025
    A 24-Gb/s/pin Single-Ended PAM-3 Transmitter With 8-bit/6-UI Encoding based partial-MTA for Low-Power Memory Interfaces
    DOI
    Jaeyoon Kim, Sanghyuk Seo, Jusung Lee, Jaekwang Yun, Suhwan Kim
    Seoul National University · Gachon University
  25. A-SSCC
    2025
    A 31.88 A /mm 2 Digital Power Delivery with Surrounding Pass-gates Architecture based on Directional-Selective Nested Quadrant Section Control in 28nm CMOS
    DOI
    Wonae Park, Junyeop Kim, Yuli Han, Gunmo Koo, Joo-Young Kim, Kunhee Cho
    Sungkyunkwan University · Seoul National University · Korea Advanced Institute of Science and Technology · Samsung
  26. A-SSCC
    2025
    An 18.4Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using 4-Phase Hybrid Timing Alignment and Dual Equalization in 1b-nm DRAM Technology
    DOI
    Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim
    SK hynix · Seoul National University
  27. CICC
    2025
    A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers
    DOI
    Jin Wang, Moxiao Lou, Zhengke Yanq, Ruijie Peng, Humiao Li, Weirong Dong, Haoran Lyu, Yida Li, Jiamin Li, Hao Yu, Jerald Yoo, Longyang Lin
    Southern University of Science and Technology · Seoul National University
  28. CICC
    2025
    A 28-nm Real-Time Reinforcement Learning Processor for Mapless Autonomous Navigation with Unified Actor-Critic Network and Inference-on-Request Scheduling
    DOI
    Juyoung Oh, Jie-Xin Liu, Yi-Chen Teng, Hsueh-Cheng Wang, Dongsuk Jeon
    Seoul National University · National Yang Ming Chiao Tung University
  29. CICC
    2025
    A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation
    DOI
    Hyun-Seok Choi, Sunki Cho, Sanghee Lee, Hyeri Roh, Jeong-Eun Song, Honggyoo Ahn, Jihee Kim, Minchang Kim, Hankyu Chi, Deog-Kyoon Jeong, Woo-Seok Choi
    Seoul National University · SK hynix
  30. CICC
    2025
    A Wireless Biopotential Sensing Node with Simultaneous Body-Channel Communication by TX-Coupled 21 Vpp Common-Mode Interference Suppression
    DOI
    Yingjie Zhu, Ruizhi Liu, Yiqing Lan, Yilong Dong, Zhenyu Guo, Ruohan Wu, Yuxin Chen, Longyang Lin, Jerald Yoo, Jiamin Li
    Southern University of Science and Technology · Seoul National University
  31. CICC
    2025
    An 83.16-TOPS/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS
    DOI
    Sangsu Jeong, Huiwon Yun, Dongkwon Lee, Sunwoo Lee, Minyoung Kang, Dongsuk Jeon
    Seoul National University
  32. CICC
    2025
    An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface
    DOI
    Giyeong Heo, Younghwan Chang, Yong-Un Jeong, Jaekwang Yun, Jusung Lee, Shin-Hyun Jeong, Sanghyuk Seo, Suhwan Kim
    Seoul National University · Samsung · Sejong University
  33. ESSERC
    2025
    Concurrent Multi-Energy Harvesting IC for Self-Sustained Biomedical Applications
    DOI
    Zhuoyue Li, Joanne Si Ying Tan, Jia Yi Fong, Yingna Huang, Astrid Rusly, Jiaer Chen, Benjamin Ho Yin Lee, Jerald Yoo
    Seoul National University · National University of Singapore
  34. ESSERC
    2025
    Falcon: An Event-Driven Object Tracking SoC with Activation-Skip and Weight-Compression MRAM PIM and Heterogenous Q/K/V Read-Only-Once Attention Flow
    DOI
    Wenao Xie, Haoyang Sang, Zhamaliddin Kalzhan, Jingu Lee, Jerald Yoo, Kangho Lee, Hoi-Jun Yoo
    Korea Advanced Institute of Science and Technology · Seoul National University · Samsung
  35. ISSCC
    2025
    22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces
    DOI
    Kahyun Kim, Jung-Hun Park, Ha-Jung Park, Jia Park, Jihee Kim, Woo-Seok Choi
    Seoul National University · University of California, Berkeley
  36. ISSCC
    2025
    22.2: An $850\mu \mathrm{W}$ 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces
    DOI
    Jeongbeom Seo, Yoonseo Cho, Yuhwan Shin, Jaehyouk Choi
    Seoul National University
  37. ISSCC
    2025
    22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces
    DOI
    Boram Kim, Hankyu Chi, Hyeongjun Ko, Sangyeon Byeon, Sungkwon Lee, Changhyun Pyo, Seulgi Kim, Byungjun Kang, Eunji Song, Kwangjin Na, Jinyoup Cha, Hyesoo Kim, Shinyoung Park, Woo-Seok Choi, Kyunghoon Kim, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim
    SK hynix · Seoul National University
  38. ISSCC
    2025
    34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration
    DOI
    Munjae Chae, Seheon Jang, Chanwoong Hwanq, Hangi Park, Jaehyouk Choi
    Seoul National University
  39. ISSCC
    2025
    8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time
    DOI
    Jaeho Kim, Myeongho Han, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
    Seoul National University · Kyung Hee University
  40. ISSCC
    2025
    A 28nm 18. $1 \mu \mathrm{J}$ /Acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assisted Computing
    DOI
    Sangsu Jeong, Sungjin Park, Mingoo Seok, Dongsuk Jeon
    Seoul National University · Columbia University
  41. JSSC
    2025
    10-GSymbols/s Supply-Modulated APSKC SiGe HBT Transmitter RF Front End for Operation at 250 GHz With 6.8-dBm Peak Modulated Power
    DOI
    Haidong Guo, Suprovo Ghosh, Frank Zhang, Suhwan Lee, Wooyeol Choi, Shenggang Dong, Ibukunoluwa Momson, Karl Strecker, Kenneth K. O
    The University of Texas at Dallas · Seoul National University · Oklahoma State University
  42. JSSC
    2025
    A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator
    DOI
    Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi
    Korea Advanced Institute of Science and Technology · Samsung · Qualcomm · Seoul National University
  43. JSSC
    2025
    A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology
    DOI
    Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo
    SK hynix · Hanyang University · Korea Electronics Technology Institute · Samsung · Gachon University · Seoul National University · Yonsei University
  44. JSSC
    2025
    A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution
    DOI
    Jihee Kim, Jia Park, Jiwon Shin, Hanseok Kim, Kahyun Kim, Haengbeom Shin, Ha-Jung Park, Woo-Seok Choi
    Seoul National University · Georgia Institute of Technology
  45. JSSC
    2025
    A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces
    DOI
    Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi
    Korea Advanced Institute of Science and Technology · Seoul National University · Samsung
  46. JSSC
    2025
    A Low-Jitter Fractional- N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration
    DOI
    Munjae Chae, Seheon Jang, Seungjae Lee, Jaehyouk Choi
    Seoul National University
  47. JSSC
    2025
    A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier
    DOI
    Seohee Jung, Jaeho Kim, Jooeun Bang, Sarang Lee, Heein Yoon, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology · Ulsan National Institute of Science and Technology
  48. JSSC
    2025
    A Rail-to-Rail Input NS-Pipelined-SAR ADC With Self-Boosted Input Impedance and Reused Residue Amplifier for Biosignal Acquisition
    DOI
    Rucheng Jiang, Jia Yi Fong, Chne-Wuen Tsai, Jiaer Chen, Zhongqi Li, Benjamin Ho Yin Lee, Jerald Yoo
    National University of Singapore · Seoul National University
  49. JSSC
    2025
    A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS
    DOI
    Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Kyogu Lee, Dongsuk Jeon
    Seoul National University · Sungkyunkwan University
  50. JSSC
    2025
    An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory
    DOI
    Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee
    Korea University · Seoul National University · Samsung · Samsung
  51. A-SSCC
    2024
    A 1.96Vpp Input-Range 3rd-order Noise-Shaping Pipelined-SAR ADC with Self-Boosted Impedance and Active Charge Sharing for Biosignal Acquisition
    DOI
    Rucheng Jiang, Chne-Wuen Tsai, Benjamin Lee Ho Yin, Jia Yi Fong, Jerald Yoo
    National University of Singapore · Seoul National University
  52. A-SSCC
    2024
    A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology
    DOI
    Hong-Seok Choi, Jae-Geon Lee, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyung-Rok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Min-Seong Choo
    SK hynix · Hanyang University · Korea Electronics Technology Institute · Samsung · University of Suwon · Seoul National University
  53. A-SSCC
    2024
    A 3-D Ising Machine with 12-Way Supply-and-Bulk Injection Locking Oscillators for Combinatorial Problem Solving
    DOI
    Jiaer Chen, Yingna Huang, Jiamin Li, Longyang Lin, Han Wu, Jerald Yoo
    National University of Singapore · Southern University of Science and Technology · Seoul National University
  54. A-SSCC
    2024
    A –51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector
    DOI
    Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology
  55. A-SSCC
    2024
    PRIM-CAEFA: A 64K-spin Packet-based Reconfigurable Ising Machine with Cross-problem Adjustment-free Energy Feedback Annealing
    DOI
    Yingna Huang, Chne-Wuen Tsai, Jiaer Chen, Zhongqi Li, Longyang Lin, Jiamin Li, Jerald Yoo
    National University of Singapore · Southern University of Science and Technology · Seoul National University
  56. CICC
    2024
    A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions
    DOI
    Eunhwan Kim, Hyunmyung Oh, Jehun Lee, Jihoon Park, Myeongeun Kwon, Jae-Joon Kim
    Pohang University of Science and Technology · Seoul National University
  57. CICC
    2024
    A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference
    DOI
    Sangsu Jeong, Juyoung Oh, Dongsuk Jeon
    Seoul National University
  58. CICC
    2024
    A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain
    DOI
    Minyoung Kang, Sunghoon Kim, Youngmin Park, Sangsu Jeong, Dongsuk Jeon
    Seoul National University
  59. CICC
    2024
    An Analog Neuromorphic On-Chip Training System with IGZO TFT-Based 6T1C 367-State Synaptic Memory Achieving 0.99-R2 Linearity and 104-Times Enhanced Retention Time
    DOI
    Minil Kang, Minseong Um, Jongun Won, Jaehyeon Kang, Sangjun Hong, Narae Han, Sangwook Kim, Sangbum Kim, Hyung-Min Lee
    Korea University · Seoul National University · Samsung · Samsung
  60. ESSERC
    2024
    A 1.22fJ/cycle 17T Pseudo-Static True Single-Phase Clock Flip-Flop in 14nm FinFET CMOS
    DOI
    Dongkwon Lee, Sunghoon Kim, Minyoung Kang, Seoyoon Jang, Sungjin Park, Jaeha Kim, Dongsuk Jeon
    Seoul National University
  61. ESSERC
    2024
    A 3.32mW 300MS/s 13b Pipelined SAR ADC Using a Time-Assisted Ringamp with Dynamic Slew Rate and Low-Supply Bias
    DOI
    Rucheng Jiang, Jerald Yoo
    National University of Singapore · Seoul National University
  62. ESSERC
    2024
    An 8 GHz 9 bit Phase-Rotating ILCM with DTC Range Reduction for High-Speed Serial Links
    DOI
    Jia Park, Jihee Kim, Sanghee Lee, Kahyun Kim, Ha-Jung Park, Woo-Seok Choi
    Seoul National University
  63. ISSCC
    2024
    10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm
    DOI
    Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology
  64. ISSCC
    2024
    10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
    DOI
    Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology
  65. JSSC
    2024
    A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation
    DOI
    Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi
    Korea Advanced Institute of Science and Technology · Qualcomm · Kyung Hee University · Seoul National University
  66. JSSC
    2024
    A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
    DOI
    Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi
    Seoul National University · Korea Advanced Institute of Science and Technology
  67. JSSC
    2024
    A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces
    DOI
    Jaekwang Yun, Sangyoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong
    Seoul National University · Samsung · Kwangwoon University · Sejong University
  68. VLSI
    2024
    A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy
    DOI
    Sungjin Park, Kwanghyun Shin, Dongkwon Lee, Minyoung Kang, Sunwoo Lee, Youngmin Park, Mingoo Seok, Dongsuk Jeon
    Seoul National University · Columbia University
  69. A-SSCC
    2023
    A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge
    DOI
    Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong
    Seoul National University · SK hynix
  70. CICC
    2023
    A 0.99μs FFT-Based Fast-Locking, 0.82GHz-to-4.1GHz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces
    DOI
    Woosong Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, Deog-Kyoon Jeong
    Seoul National University
  71. ESSERC
    2023
    A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array
    DOI
    Sunwoo Lee, Jeongwoo Park, Dongsuk Jeon
    Seoul National University · Sungkyunkwan University
  72. ESSERC
    2023
    A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM
    DOI
    Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi
    Seoul National University
  73. ISSCC
    2023
    22.8 A0.81 mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS
    DOI
    Sungjin Park, Sunwoo Lee, Jeongwoo Park, Hyeong-Seok Choi, Dongsuk Jeon
    Seoul National University
  74. ISSCC
    2023
    A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS
    DOI
    Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong
    Seoul National University
  75. JSSC
    2023
    A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces
    DOI
    Yong-Un Jeong, Joo-Hyung Chae, Suhwan Kim
    Sejong University · Kwangwoon University · Seoul National University
  76. JSSC
    2023
    A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
    DOI
    Woosong Jung, Kwangho Lee, Kwanseo Park, Haram Ju, Jinhyung Lee, Deog-Kyoon Jeong
    Seoul National University · Korea Electronics Technology Institute · Yonsei University · SK hynix
  77. JSSC
    2023
    A Wideband LO Generator for 5G FR1 Bands Using a Single LC -VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
    DOI
    Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi
    Korea Advanced Institute of Science and Technology · Kyung Hee University · Seoul National University
  78. JSSC
    2023
    An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
    DOI
    Jonghyun Oh, Young-Ha Hwang, Jun-Eun Park, Mingoo Seok, Deog-Kyoon Jeong
    Columbia University · Soongsil University · Sungkyunkwan University · Seoul National University
  79. A-SSCC
    2022
    A 0.0043-mm2 Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO Using Load-Direct Droop Detector and Time-Based Load-State Decision
    DOI
    Jonghyun Oh, Yoonho Song, Young-Ha Hwang, Jun-Eun Park, Mingoo Seok, Deog-Kyoon Jeong
    Columbia University · Seoul National University · Soongsil University · Chungnam National University
  80. A-SSCC
    2022
    A 10Gb/s/pin DQS and WCK Built-Out Tester for LPDDR5 DRAM Test
    DOI
    Chan-Ho Kye, Jihee Kim, Kyungmin Baek, Kahyun Kim, Sangjin Pack, Changwon Jung, Deog-Kyoon Jeong
    École Polytechnique Fédérale de Lausanne · Seoul National University · SK hynix
  81. A-SSCC
    2022
    A 42Gb/s PAM-8 Transmitter with Feed-Forward Tomlinson-Harashima Precoding in 28nm CMOS
    DOI
    Byungjun Kang, Woosong Jung, Hyojun Kim, Sanghee Lee, Deog-Kyoon Jeong
    Seoul National University
  82. ESSERC
    2022
    A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training
    DOI
    Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon
    Seoul National University
  83. ESSERC
    2022
    A 40nm 5.6TOPS/W 239GOPS/mm2 Self-Attention Processor with Sign Random Projection-based Approximation
    DOI
    Seong Hoon Seo, Soosung Kim, Sung Jun Jung, Sangwoo Kwon, Hyunseung Lee, Jae W. Lee
    Seoul National University
  84. ESSERC
    2022
    A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration
    DOI
    Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong
    Seoul National University · Hanyang University
  85. ISSCC
    2022
    A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration
    DOI
    Hyojun Kim, Hyeong-Seok Oh, Woosong Jung, Yoonho Song, Jonghyun Oh, Deog-Kyoon Jeong
    Seoul National University · University of California, Berkeley · Columbia University
  86. ISSCC
    2022
    A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
    DOI
    Sangyoon Lee, Jaekwang Yun, Suhwan Kim
    Seoul National University
  87. JSSC
    2022
    A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
    DOI
    Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong
    Seoul National University · SK hynix
  88. JSSC
    2022
    A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees
    DOI
    Jeongwoo Park, Sunwoo Lee, Dongsuk Jeon
    Seoul National University
  89. JSSC
    2022
    A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns
    DOI
    Young-Ha Hwang, Jonghyun Oh, Woo-Seok Choi, Deog-Kyoon Jeong, Jun-Eun Park
    Harvard University · Columbia University · Seoul National University · Chungnam National University
  90. JSSC
    2022
    BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
    DOI
    Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim
    Soongsil University · Pohang University of Science and Technology · Samsung · Seoul National University
  91. JSSC
    2022
    Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
    DOI
    Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong
    Korea Electronics Technology Institute · SK hynix · Yonsei University · Seoul National University
  92. JSSC
    2022
    Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector
    DOI
    Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong
    University of California, Berkeley · Seoul National University
  93. VLSI
    2022
    0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link
    DOI
    Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong
    Seoul National University · SK hynix · Samsung
  94. VLSI
    2022
    A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller
    DOI
    Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong
    Seoul National University · Columbia University