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企業・研究機関Company / Institute · 中国China · 2022–2026 LIVE

Shanghai Zhangjiang Laboratory

中国China 4位 (37.5 pt) · 世界World 28位 (0 pt) · 対象論文Papers 8

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0123202220232024 VLSI: 12024 JSSC: 12024 A-SSCC: 1320242025 JSSC: 12025 A-SSCC: 1220252026 ISSCC: 22026 JSSC: 132026
ISSCCVLSIJSSCA-SSCC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC––––2
VLSI––1––
JSSC––111
A-SSCC––11–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1200.11中国China #6 · 世界World #52
VLSI Tier 1100.20中国China #5 · 世界World #48
JSSC Tier 1300.29中国China #4 · 世界World #47
CICC Tier 2000.00–
A-SSCC Tier 2200.11中国China #3 · 世界World #11
ESSERC Tier 2000.00–

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. ISSCC
    2026
    A 1.2GHz 12.77GB/s/mm 2 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications
    DOI
    Yue Cao, Jinghao Jiang, Haijun Jiang, Qian Zhang, Xuanzhi Liu, Jinhui Cheng, Zhongze Han, Xiping Jiang, Fengguo Zuo, Song Wang, Fujun Bai, Yixin Guo, Chunmeng Dou, Jianguo Yang, Hangbing Lv, Qi Liu, Ming Liu
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory · Chinese Academy of Sciences · Xi'an UniIC Semiconductors (China)
  2. ISSCC
    2026
    A 16Gb/s/pin 0.51pJ/b Single-Ended NRZ Transceiver with Distributed Dual-Loop V DDQ -Ripple Compensation and Dynamic Clock Duty-Cycle Calibration for Memory Interfaces
    DOI
    Yuchen He, Yunbin Luo, Yunzhengmao Wang, Tengyue Yi, Chen Jiang, Chixiao Chen, Qi Liu, Ming Liu, Wenning Jiang
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory
  3. JSSC
    2026
    A Comprehensive Analysis and Chip Implementation of Hybrid-Bonding-Based 3D-DRAM Process-Near-Memory Design for LLM Inference
    DOI
    Yue Cao, Jinghao Jiang, Haijun Jiang, Qian Zhang, Xiping Jiang, Fengguo Zuo, Song Wang, Fujun Bai, Yixin Guo, Chunmeng Dou, Jianguo Yang, Hangbing Lv, Qi Liu, Ming Liu
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory · Xi'an UniIC Semiconductors (China) · Chinese Academy of Sciences
  4. A-SSCC
    2025
    LoRA-CIM: A Fully-Digital Hybrid Flash-SRAM CIM Accelerator with LoRA Fine-Tuned LLM in Edge Devices
    DOI
    Zhiwang Guo, Taoran Shen, Jinbei Fang, Jingwen Jiang, Deyang Chen, Hong Nie, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory
  5. JSSC
    2025
    A 28-nm RRAM/SRAM Collaborative CIM Accelerator Supporting RRAM-Endurance-Latency Awareness for Edge Fine-Tuning
    DOI
    Chen Mu, Zhirui Huang, Hao Jiang, Jie Liao, Yuliang Zhou, Liang Chen, Yechu Zhang, Haozhe Zhu, Jianguo Yang, Qi Liu, Chixiao Chen
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory
  6. A-SSCC
    2024
    A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer
    DOI
    Chen Mu, Zhirui Huang, Hao Jiang, Jie Liao, Bo Jiao, Yuliang Zhou, Haozhe Zhu, Jianguo Yang, Qi Liu, Chixiao Chen
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory
  7. JSSC
    2024
    A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier
    DOI
    Qiqiao Wu, Yue Cao, Qing Luo, Haijun Jiang, Zhongze Han, Yongkang Han, Chunmeng Dou, Hangbing Lv, Qi Liu, Jianguo Yang, Ming Liu
    Chinese Academy of Sciences · Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory · University of Chinese Academy of Sciences
  8. VLSI
    2024
    A 67F2 Reconfigurable PUF Using 1T2R RRAM Switching Competition in 28nm CMOS with 5e-9 Bit Error Rate
    DOI
    Yue Cao, Honghu Yang, Jianguo Yang, Qi Liu, Ming Liu
    Fudan University · Shanghai Zhangjiang Laboratory · Zhangjiang Laboratory