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大学University · ドイツGermany · 2022–2026 LIVE

Technische Universität Berlin

世界World 25位 (0 pt) · 対象論文Papers 12

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

012342022 CICC: 1120222023 VLSI: 12023 JSSC: 12023 ESSERC: 2420232024 ESSERC: 1120242025 CICC: 12025 ESSERC: 1220252026 ISSCC: 12026 JSSC: 12026 CICC: 242026
ISSCCVLSIJSSCCICCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC––––1
VLSI–1–––
JSSC–1––1
CICC1––12
ESSERC–211–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1111.00世界World #112
VLSI Tier 1111.00世界World #78
JSSC Tier 1222.00世界World #146
CICC Tier 2443.13世界World #52
A-SSCC Tier 2000.00–
ESSERC Tier 2443.21世界World #42

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A 25GS/s Single Track and Hold with 65GHz Bandwidth Featuring 38.8dB SNDR and 50.6dBc SFDR at 50.7GHz Input in 22nm CMOS
    DOI
    Marcel Runge, Daniel Lobitz, Ols Hidri, Ingo Dettmann, Thorsten Siera, Friedel Gerfers
    Technische Universität Berlin · Rohde & Schwarz (Germany)
  2. CICC
    2026
    A SST-DAC Back-Gate Calibrated 5 GS/s CT Sigma Delta Modulator With 83 MHz BW, 100 dB SFDR and –95 dBc IM3 in 22 nm FD-SOI
    DOI
    Julius Edler, Marcel Runge, Enne Wittenhagen, Chen-Chun Hsu, Frowin Buballa, Patrick Artz, Nikolaos Kioulos, Friedel Gerfers
    Technische Universität Berlin
  3. ISSCC
    2026
    A 2×2 10GS/s TTD BF Receiver Utilizing Charge-Based Summation with 10.5GHz Bandwidth and SNDR/SFDR with 49.5dB/57.5dBc in 22nm CMOS
    DOI
    Enne Wittenhagen, Dominik Wilding, Patrick Artz, Sebastian Linnhoff, Philipp Scholz, Friedel Gerfers
    Technische Universität Berlin
  4. JSSC
    2026
    Integrator Linearization Technique Using Active Back-Gate Control in a 4.4 GS/s 220 MHz Bandwidth CT Sigma–Delta ADC
    DOI
    Julius Edler, Marcel Runge, Christian Rudorf, Jenny Lichtenstein, Philipp Nickel, Friedel Gerfers
    Technische Universität Berlin
  5. CICC
    2025
    A DAC-based Transmitter with VCSEL Bias-Current Generation enabling 180 Gbit/s PAM-8 Electrical and 100 Gbit/s PAM-4 VCSEL-based Transmission in 22nm SOI
    DOI
    Urs Hecht, Philipp Scholz, Patrick Kurth, Frowin Buballa, Helia Ordouei, Friedel Gerfers
    Technische Universität Berlin
  6. ESSERC
    2025
    A 20 GS/s 46 dB SNDR 16x Time-Interleaved Pipelined-SAR ADC Using Bulk Calibration for Comparator Offset and Bandwidth Mismatch
    DOI
    Patrick J. Artz, Qihang He, Sebastian Linnhoff, Frowin Buballa, Marcel Runge, Enne Wittenhagen, Philipp Scholz, Friedel Gerfers
    Technische Universität Berlin
  7. ESSERC
    2024
    A Single-Stage Inverter Based OTA Using Back-Gate Gain Boosting in 22nm FDSOI CMOS
    DOI
    Marcel Runge, Jendrik Kellermann, Philipp Scholz, Enne Wittenhagen, Friedel Gerfers
    Technische Universität Berlin
  8. ESSERC
    2023
    On the Noise Contribution of Dielectric Interfaces in Biochemical CMOS Sensor Chips
    DOI
    Mathias Schulz, Stefan Keil, Simon Löhlein, Sourish Banerjee, Nicolai Simon, Catherine Dubourdieu, Volker Bucher, Roland Thewes
    Technische Universität Berlin · Helmholtz-Zentrum Berlin für Materialien und Energie · Furtwangen University
  9. ESSERC
    2023
    True Voltage-Mode NRZ VCSEL Transmitter enabling 60 Gbit/s at 0.37 pJ/bit in 22 nm FDSOI
    DOI
    Urs Hecht, Helia Ordouei, Nikolay Ledentsov, Philipp Scholz, Patrick Kurth, Nikolay Ledentsov, Friedel Gerfers
    Technische Universität Berlin · Vertically Integrated Systems (Germany)
  10. JSSC
    2023
    An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter
    DOI
    Marcel Runge, Julius Edler, Tobias Kaiser, Kai Misselwitz, Friedel Gerfers
    Technische Universität Berlin
  11. VLSI
    2023
    A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter
    DOI
    Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers
    Technische Universität Berlin
  12. CICC
    2022
    A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS
    DOI
    Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers
    Technische Universität Berlin