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JSSC · 2022–2026 LIVE

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対象論文Papers 31 · 筆頭著者first author 2 · 著者按分fractional 11.57 · 台湾Taiwan #1 · 世界World #5

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Win-San Khwa ORCID18
2Yu-Der Chih17
3Meng-Fan Chang ORCID15
4Tsung-Yung Jonathan Chang ORCID14
5Hong-Chen Cheng5
5Hung-Jen Liao5
7Muya Chang ORCID4
8Ashwin Sanjay Lele ORCID3
8Bo Zhang3
8Chi-Shi Chen3
8Chun-Pin Lin3
8Hidehiro Fujiwara ORCID3
8Isabel Wang3
8Jui-Jen Wu ORCID3
8Liang-Yi Lin3
8Nian-Shyang Chang3
8Ping-Sheng Wu ORCID3
8Wen-Ching Chen3
8Yih Wang3
8Yu-Hao Hsu3
21Brian Crafton ORCID2
22Carlos H. Diaz1
22Chao-Kai Chuang1
22Cheng-En Lee1
22Chia-Fu Lee1
22Chia-Jung Tsen1
22Chieh-Pu Lo ORCID1
22Chien-Yu Huang1
22Chin-I Su1
22Chung-Cheng Chou1
22Harry Chuang1
22Haruki Mori ORCID1
22Je-Min Hung ORCID1
22Jhon-Jhy Liaw1
22Jun Cheng Liu1
22Kang-Hui Peng1
22Kinshuk Khare1
22Koji Nii ORCID1
22Leo Liu1
22Masaru Haraguchi ORCID1
22Ming-Hung Chang1
22Ping-Chun Wu ORCID1
22Quincy Li1
22Shien-Yang Wu1
22Shih-Hsin Teng1
22Tan-Li Chou1
22Ted Chu ORCID1
22Tung-Cheng Chang1
22Tz-Wun Wang ORCID1
22Wei-Chang Zhao1
22Yen-Chi Chou1
22Yen-Huei Chen ORCID1
22Yi-Chun Shih ORCID1
22Yorinobu Fujino1
22Yoshisato Yokoyama ORCID1

対象論文Papers

  1. JSSC
    2026
    A 13.8% Speed-Enhanced 1 T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Koji Nii, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  2. JSSC
    2026
    A 3 nm Fin-FET 19.87-Mbit/mm 2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  3. JSSC
    2026
    A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
    DOI
    Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  4. JSSC
    2026
    A 3-nm FinFET 563-kbit 35.5-Mbit/mm 2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  5. JSSC
    2026
    A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models
    DOI
    Che-Kai Liu, Zishen Wan, Young-Seok Noh, Mohamed Ibrahim, Samuel D. Spetalnick, Tushar Krishna, Win-San Khwa, Ashwin Sanjay Lele, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC · TSMC
  6. JSSC
    2026
    A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device
    DOI
    Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Industrial Technology Research Institute
  7. JSSC
    2026
    A Nonvolatile AI-Edge Processor With Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro Using Dynamic Floating-/Fixed-Point Accumulation
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  8. JSSC
    2026
    A Versatile-Format Dual-Representation Gain-Cell Computing-in-Memory Accelerator for General-Purpose Edge AI Tasks
    DOI
    Jen-Chun Tien, De-Qi You, Win-San Khwa, Yu-Sheng Kao, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  9. JSSC
    2026
    A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  10. JSSC
    2026
    FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing
    DOI
    Weihong Xu, Chang Eun Song, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Tajana Rosing, Mingu Kang
    University of California San Diego · TSMC
  11. JSSC
    2026
    Monolithic GaN-Based Secondary-Side Controller for Precise Dead-Time Control Enabling ZVS and ZCS
    DOI
    Chi-Yu Chen, Po-Jui Chiu, Yu-Ting Huang, Xiao-Quan Wu, Chien-Wei Cho, Sheng-Hsi Hung, Tz-Wun Wang, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Shian-Ru Lin, Hann-Huei Tsai
    National Yang Ming Chiao Tung University · TSMC · Realtek
  12. JSSC
    2026
    PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI
    DOI
    Luqi Zheng, Amir Massah Bavani, Mufeng Chen, Shuting Du, Te-Yu Hsin, Win-San Khwa, Ping-Sheng Wu, Ashwin Sanjay Lele, Bo Zhang, Brian Crafton, Harry Chuang, Yu-Der Chih, Meng-Fan Chang, Haitong Li
    Purdue University West Lafayette · TSMC
  13. JSSC
    2025
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  14. JSSC
    2025
    A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device
    DOI
    Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Georgia Institute of Technology · TSMC
  15. JSSC
    2025
    A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots
    DOI
    I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · TSMC
  16. JSSC
    2025
    A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
    DOI
    Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  17. JSSC
    2025
    An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance
    DOI
    Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC · Korea Aerospace University · Daegu Gyeongbuk Institute of Science and Technology
  18. JSSC
    2025
    An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips
    DOI
    Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Industrial Technology Research Institute
  19. JSSC
    2025
    MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator
    DOI
    Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC
  20. JSSC
    2024
    A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality
    DOI
    Wen-Cong Huang, I-Ting Lin, Ying-Sheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · MediaTek · University of California, Berkeley · TSMC
  21. JSSC
    2024
    A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices
    DOI
    Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · MediaTek · TSMC
  22. JSSC
    2024
    A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  23. JSSC
    2024
    A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking
    DOI
    Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC
  24. JSSC
    2024
    A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme
    DOI
    Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  25. JSSC
    2024
    An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices
    DOI
    De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chi-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  26. JSSC
    2024
    EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
    DOI
    Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina
    Stanford University · TSMC
  27. JSSC
    2023
    8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices
    DOI
    Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  28. JSSC
    2022
    A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device
    DOI
    Yen-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng-Fan Chang
    National Tsing Hua University · TSMC · University of Florida
  29. JSSC
    2022
    A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding
    DOI
    Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · Daegu Gyeongbuk Institute of Science and Technology · TSMC
  30. JSSC
    2022
    A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection
    DOI
    Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · Daegu Gyeongbuk Institute of Science and Technology · TSMC
  31. JSSC
    2022
    CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference
    DOI
    Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guenole Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC · Meta