TopSSCS
← 総合ランキングへ戻るBack to overall ranking

企業・研究機関Company / Institute · 台湾Taiwan · 2022–2026 LIVE

TSMC

台湾Taiwan 1位 (105.5 pt) · 世界World 5位 (43 pt) · 対象論文Papers 111

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0510152025302022 ISSCC: 72022 VLSI: 42022 JSSC: 42022 CICC: 12022 A-SSCC: 11720222023 ISSCC: 82023 VLSI: 82023 JSSC: 12023 ESSERC: 11820232024 ISSCC: 102024 VLSI: 72024 JSSC: 72024 A-SSCC: 12024 ESSERC: 12620242025 ISSCC: 102025 VLSI: 82025 JSSC: 72025 CICC: 12025 A-SSCC: 12025 ESSERC: 12820252026 ISSCC: 42026 VLSI: 62026 JSSC: 12222026
ISSCCVLSIJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC7810104
VLSI48786
JSSC417712
CICC1––1–
A-SSCC1–11–
ESSERC–111–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1392020.13台湾Taiwan #1 · 世界World #3
VLSI Tier 1331621.69台湾Taiwan #1 · 世界World #3
JSSC Tier 131211.57台湾Taiwan #1 · 世界World #5
CICC Tier 2221.50台湾Taiwan #1 · 世界World #13
A-SSCC Tier 2301.42台湾Taiwan #2 · 世界World #7
ESSERC Tier 2300.99台湾Taiwan #2 · 世界World #22

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. ISSCC
    2026
    15.4 A 16nm 168Mb Embedded STT-MRAM with 0.0249µm 2 Bit-Cell, Dual-Port Access, and 51.2Gb/s Read Throughput for Automotive and Edge AI Applications
    DOI
    Po-Hao Lee, Chia-Fu Lee, Hon-Jarn Lin, Cheng-Han Lu, Yen-An Chang, Pranata W. Sanjaya, Chia-Jung Tsen, Kuan-Chun Chen, Ming-Chieh Lin, Chao-Jung Hung, Tan-Li Chou, Chih-Hui Weng, Chia-Yu Wang, J.J. Wu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
    TSMC
  2. ISSCC
    2026
    30.5 A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks
    DOI
    Jen-Chun Tien, Win-San Khwa, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Yu-Sheng Kao, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, De-Qi You, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  3. ISSCC
    2026
    8.2 A 32Gb/s 12.35Tb/s/mm 2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging
    DOI
    Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh
    TSMC · TSMC
  4. ISSCC
    2026
    A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN
    DOI
    Hung-Hsi Hsu, Win-San Khwa, Yao-Kai Yeh, Chih-Ling Wu, Chang-Yuan Chen, Yen-Che Huang, Yen-Hua Lin, Cheng-Feng Chang, Yen-Tung Shao, Jen-Chun Tien, De-Qi You, Ping-Sheng Wu, Bo Zhang, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  5. JSSC
    2026
    A 13.8% Speed-Enhanced 1 T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Koji Nii, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  6. JSSC
    2026
    A 3 nm Fin-FET 19.87-Mbit/mm 2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  7. JSSC
    2026
    A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
    DOI
    Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  8. JSSC
    2026
    A 3-nm FinFET 563-kbit 35.5-Mbit/mm 2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  9. JSSC
    2026
    A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models
    DOI
    Che-Kai Liu, Zishen Wan, Young-Seok Noh, Mohamed Ibrahim, Samuel D. Spetalnick, Tushar Krishna, Win-San Khwa, Ashwin Sanjay Lele, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC · TSMC
  10. JSSC
    2026
    A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device
    DOI
    Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Industrial Technology Research Institute
  11. JSSC
    2026
    A Nonvolatile AI-Edge Processor With Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro Using Dynamic Floating-/Fixed-Point Accumulation
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  12. JSSC
    2026
    A Versatile-Format Dual-Representation Gain-Cell Computing-in-Memory Accelerator for General-Purpose Edge AI Tasks
    DOI
    Jen-Chun Tien, De-Qi You, Win-San Khwa, Yu-Sheng Kao, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  13. JSSC
    2026
    A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  14. JSSC
    2026
    FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing
    DOI
    Weihong Xu, Chang Eun Song, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Tajana Rosing, Mingu Kang
    University of California San Diego · TSMC
  15. JSSC
    2026
    Monolithic GaN-Based Secondary-Side Controller for Precise Dead-Time Control Enabling ZVS and ZCS
    DOI
    Chi-Yu Chen, Po-Jui Chiu, Yu-Ting Huang, Xiao-Quan Wu, Chien-Wei Cho, Sheng-Hsi Hung, Tz-Wun Wang, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Shian-Ru Lin, Hann-Huei Tsai
    National Yang Ming Chiao Tung University · TSMC · Realtek
  16. JSSC
    2026
    PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI
    DOI
    Luqi Zheng, Amir Massah Bavani, Mufeng Chen, Shuting Du, Te-Yu Hsin, Win-San Khwa, Ping-Sheng Wu, Ashwin Sanjay Lele, Bo Zhang, Brian Crafton, Harry Chuang, Yu-Der Chih, Meng-Fan Chang, Haitong Li
    Purdue University West Lafayette · TSMC
  17. VLSI
    2026
    A $\mathbf{2 n m}$ 37.4 Mbit $/ \text{mm}^{2}$ Dual-Rail SRAM with Row-Access Aware Read Tracking and Write Assist Circuits Enabling 2.28 pJ/Access Energy Efficient Operation
    DOI
    Ryo Takamatsu, Makoto Yabuuchi, Masaya Hamada, Tomotaka Tanaka, Shu-Huan Hsu, Yao-Yi Liu, Yuichiro Ishii, Koji Nii, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  18. VLSI
    2026
    A $\mathbf{2 n m}$ Nanosheet $\mathbf{1 2 8 K b}$ Anti-Fuse One-Time-Programmable Memory Featuring Core-Transistor-Only High Voltage Program Circuit and Fault-Tolerant Design
    DOI
    Gu-Huan Li, Wan-Hsueh Cheng, Chen-Wei Liang, Shaun Chou, Perng-Fei Yuh, Li-Yu Yeh, Yen-Hsiang Huang, Yi-Ching Liu, Chungi Huang, Duncan Yang, Yih Wang, Tsung-Yung Jonathan Chang, Lien-Jung Hung, Ping-Wei Wang, Chin-Shan Hou, Hsin-Jou Chuang, An-Shun Teng, Li-Ling Luo, Jordan Hsu
    TSMC
  19. VLSI
    2026
    A 0.75V, 1.43%-Inaccuracy 4T MOS-Based Voltage Reference in $251 \mu \mathrm{m}^{2}$ Area
    DOI
    Szu-Lin Liu, Bei-Shing Lien, Wie-Lin Lai, Yi-Chen Lu, Ching-Lin Jen, Yung-Chow Peng, Kenny Cheng-Hsiang Hsieh
    TSMC
  20. VLSI
    2026
    A 25.3% Area-Efficient 1CPP Mask ROM with Robust Power Mesh on 2-nm NanoSheet Logic CMOS
    DOI
    Ryota Watanabe, Kazumasa Uno, Hidemitsu Kojima, Ayumu Yamada, Hiromasa Otsubo, Ted Chu, Tsung-Hsien Huang, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  21. VLSI
    2026
    A 2nm 234.4 TOPS/W and 511.9 $\text{TOPS}/\text{mm}^{2}$ Digital Computing-in-Memory Compiler with Multiple MAC Units per Weight and Multiple Data Format Support
    DOI
    Hidehiro Fujiwara, Brian Crafton, Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Ashwin Sanjay LeLe, Bo Zhang, Chao-Kai Chuang, Hiroaki Ishii, Cheng-En Lee, Vineet Joshi, Xiaochen Peng, Xiaoyu Sun, Shu-Huan Hsu, Yao-Yi Liu, Takeshi Hashizume, Yu-Hao Hsu, Win-San Khwa, Saman Adham, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Kerem Akarvardar, Meng-Fan Chang, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  22. VLSI
    2026
    µAgent: A 7nm 404.3mJ/Action Edge SoC for Agentic AI Reasoning with Adaptive Block-Wise Mixed-Format 4-Bit Quantization and Decoupled Access-Execute
    DOI
    Wonsuk Jang, Christian Kubicka, Allen Pan, Pullabhatla Smriti, Win-San Khwa, Meng-Fan Chang, Priyanka Raina, Thierry Tambe
    Stanford University · TSMC
  23. A-SSCC
    2025
    CENTAUR: A 38.5-TFLOPS/W 600MHz Floating-Point Digital Compute-In-Memory Engine with 40nm Fusion RRAM-eDRAM Macros Featuring 3D-MAC Operation
    DOI
    Luqi Zheng, Amir Massah Bavani, Shuting Du, Te-Yu Hsin, Mufeng Chen, Win-San Khwa, Ashwin Lele, Harry Chuang, Yu-Der Chih, Meng-Fan Chang, Haitong Li
    Purdue University West Lafayette · TSMC · TSMC
  24. CICC
    2025
    UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies
    DOI
    Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Wei-Chih Chen, Hsin-Hung Kuo, Shu-Chun Yang, Shenggao Li
    TSMC · TSMC
  25. ESSERC
    2025
    A 16nm Fully Integrated SoC for Hardware-Aware Neural Architecture Search
    DOI
    Yu-Cheng Lin, Ming-Shan Huang, Jeng-Bang Wang, Wen-Ching Chen, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Tzi-Dar Chiueh, Chia-Hsiang Yang
    National Taiwan University · TSMC
  26. ISSCC
    2025
    14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  27. ISSCC
    2025
    14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices
    DOI
    Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    TSMC · National Tsing Hua University · TSMC
  28. ISSCC
    2025
    2.5 A 16nm 5.7TOPS CNN Processor Supporting Bi-Directional FPN for Small-Object Detection on High-Resolution Videos
    DOI
    Yu-Chun Ding, Chia-Yu Chang, Chun-Yeh Lin, Hui-Yun Tsai, Hao-Jiun Tu, Kai-Feng Chang, Yu-Ching Su, Tsung-Han Hsieh, Yu-Kuan Jian, Wen-Ching Chen, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chao-Tsung Huang
    National Tsing Hua University · TSMC
  29. ISSCC
    2025
    2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming
    DOI
    Kai-Ping Lin, Tong Wu, Chang-Pao Lin, Po-Wei Chen, Zhi-Jun Zhang, Win-San Khwa, Meng-Fan Chang, Chao-Tsung Huang
    National Tsing Hua University · TSMC
  30. ISSCC
    2025
    29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme
    DOI
    Hidehiro Fujiwara, Wei-Chang Zhao, Kinshuk Khare, Yi-Hsin Nien, Chih-Yu Lin, Cheng-Han Lin, Shan-Ru Liao, Kenta Torigoe, Shirleen Xia, Yuichiro Ishii, Yao-Yi Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC（日本拠点）TSMC Japan
  31. ISSCC
    2025
    32.6 A Dynamic-RON-Diminished Bidirectional GaN Load Switch with Inrush Current Protection and Spike Attenuation
    DOI
    Po-Jui Chiu, Tz-Wun Wang, Xiao-Quan Wu, Chi-Yu Chen, Yu-Ting Huang, Chien-Wei Cho, Sheng-Hsi Hung, Yu-Tse Shih, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Hann-Huei Tsai
    National Yang Ming Chiao Tung University · Realtek · TSMC
  32. ISSCC
    2025
    36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating
    DOI
    Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan Drake, Chin-Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem
    TSMC · TSMC · TSMC · AMD
  33. ISSCC
    2025
    4.6 A 0.8V, 31ppm/°C, −40dB DC-to-GHz Power-Supply-Rejection Standard-Vth Core-MOS-Only Voltage Reference with a 294µm2Area
    DOI
    Bei-Shing Lien, Szu-Lin Liu, Wei-Lin Lai, Yi-Chen Lu, Yung-Chow Peng, Kenny Cheng-Hsiang Hsieh
    TSMC
  34. ISSCC
    2025
    A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
    DOI
    Tsung-Yung Jonathan Chang, Yen-Huei Chen, K. Venkateswara Reddy, Nikhil Puri, Teja Masina, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Ku-Feng Lin, Ming-Hung Chang, Ching Wei Wu, Robin Lee, Yih Wang, Hung-Jen Liao, Quincy Li, Ping Wei Wang, Geoffrey Yeap
    TSMC
  35. ISSCC
    2025
    An Accurate Secondary-Side Controller with GaN-8ased CGS Isolated Driver Achieving Sub-1% Error On-Chip Sensing
    DOI
    Chi-Yu Chen, Tz-Wun Wang, Po-Jui Chiu, Yu-Ting Huang, Xiao-Quan Wu, Chien-Wei Cho, Sheng-Hsi Hung, Yu-Tse Shih, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Hann-Huei Tsai
    National Yang Ming Chiao Tung University · Realtek · TSMC
  36. JSSC
    2025
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  37. JSSC
    2025
    A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device
    DOI
    Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Georgia Institute of Technology · TSMC
  38. JSSC
    2025
    A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots
    DOI
    I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · TSMC
  39. JSSC
    2025
    A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
    DOI
    Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  40. JSSC
    2025
    An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance
    DOI
    Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC · Korea Aerospace University · Daegu Gyeongbuk Institute of Science and Technology
  41. JSSC
    2025
    An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips
    DOI
    Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Industrial Technology Research Institute
  42. JSSC
    2025
    MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator
    DOI
    Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC
  43. VLSI
    2025
    A 13.8% Speed-Enhanced 1T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  44. VLSI
    2025
    A 22nm 41.8TFLOPS/W AI-Edge Transformer/CNN Nonvolatile-Processor Using QKV-Softmax-Layer-Fused Hybrid ReRAM-CIM and Concurrent-Transpose/Non-Transpose SRAM-CIM
    DOI
    Hung-Hsi Hsu, Win-San Khwa, Tai-Hao Wen, Wei-Ting Hsu, Yu-Chen Chang, Hsin-Yin Lu, Hua-Jin Wen, Chang-Yuan Chen, Yen-Che Huang, Chih-Ling Wu, Ping-Sheng Wu, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · National Chung Hsing University
  45. VLSI
    2025
    A 3nm 125 Tops/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8 and FP16 Digital-CIM Compiler with Multi-Weight Update/Cycle
    DOI
    Haruki Mori, J-M. Hung, W-C. Zhao, K. Khare, B. Crafton, H. Ishii, C-E. Lee, X. Peng, X. Sun, Y. Fujino, C-J. Tsen, V. Joshi, C-K. Chuang, T. Hashizume, C-F. Lee, T-L. Chou, K. Akarvardar, S. Adham, Y. Wang, H. Fujiwara, Y-D. Chih, Y-H. Chen, H-J. Liao, T-Y. Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  46. VLSI
    2025
    A 3nm FinFET 563kbit 35.5Mbit/mm2 Dual-Rail SRAM with 3.89pJ/Access High Energy Efficient andμW/Mbit 1-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Koji Nii, Mark Zhou, J.C. Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  47. VLSI
    2025
    A CMOS-Compatible 12nm 8Mb MLC RRAM Enabling Producible 2-Bit Per Cell for High Energy Efficiency Compute-In-Memory in Edge AI Applications
    DOI
    C.Y. Tsai, S.F. Liu, J.H. Hsuen, Brian Lin, C.R. Hsieh, C.W. Chan, C.Y. Chang, Y.C. Huang, Julien Yang, J.J. Wu, Y.W. Chen, M.F. Chang, Y.D. Chih, W.T. Chu, K.C. Huang, Harry Chuang
    TSMC
  48. VLSI
    2025
    A Prototype 16Mbit RRAM on 55nm BCD with 56% Compact-Area Wordline Driver and Constant Write-Current Scheme for Automotive 150°C Operation
    DOI
    Kohei Santo, Masayoshi Nakayama, Reiji Mochida, Hitoshi Suwa, Motoki Tamura, Atsuo Mangyo, Koji Nii, Yu-Cheng Lin, C.F. Wang, Wu-Chin Tsai, Y.D. Chih, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  49. VLSI
    2025
    Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-Efficient Hyperdimensional Computing via Progressive Search
    DOI
    Chang Eun Song, Weihong Xu, Keming Fan, Soumil Jain, Gopabandhu Hota, Haichao Yang, Leo Liu, Kerem Akarvardar, Meng-Fan Chang, Carlos H. Diaz, Gert Cauwenberghs, Tajana Rosing, Mingu Kang
    University of California San Diego · TSMC
  50. VLSI
    2025
    Compact, Low-Loss, Cost-Effective, CMOS Embedded RF Switch Solution Achieving DC-100GHz True-Time Delay Phase Shifter by Phase Change Material
    DOI
    H.J. Li, K.P. Chang, C.E. Chen, Y.T. Lin, C.C. Huang, Y.W. Wang, W.F. Chen, H.Y. Chen, C.R. Hsieh, Z.H. Ya, H.H. Wang, Y.W. Ting, K.C. Tseng, Z. M. Tsai, K.C. Huang, Harry Chuang
    TSMC · National Yang Ming Chiao Tung University
  51. A-SSCC
    2024
    A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks
    DOI
    I-Hsuan Liu, I-Ting Lin, Yueh-Feng Tsai, Jeng-Sheng Hsieh, Vincent Chen, Chuei-Tang Wang, Chia-Hsiang Yang, Douglas C. H. Yu
    National Taiwan University · TSMC
  52. ESSERC
    2024
    A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC
    DOI
    Kota Shiba, Zhijie Zhan, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    TSMC（日本拠点）TSMC Japan · 東京大学The University of Tokyo · TSMC
  53. ISSCC
    2024
    1.1 Semiconductor Industry: Present & Future
    DOI
    Kevin Zhang
    TSMC
  54. ISSCC
    2024
    15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture
    DOI
    Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  55. ISSCC
    2024
    15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C
    DOI
    Yi-Cheng Huang, Shang-Hsuan Liu, Hsu-Shun Chen, Hsin-Chang Feng, Chih-Feng Li, Chou-Ying Yang, Wei-Keng Chang, Chang-Feng Yang, Chun-Yu Wu, Yen-Cheng Lin, Tsung-Tse Yang, Chih-Yang Chang, Wen-Ting Chu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
    TSMC
  56. ISSCC
    2024
    15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10 12 Write Endurance and Integrated Margin-Expansion Schemes
    DOI
    Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC
  57. ISSCC
    2024
    20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices
    DOI
    Ming-En Shih, Shih-Wei Hsieh, Ping-Yuan Tsai, Ming-Hung Lin, Pei-Kuei Tsung, En-Jui Chang, Jenwei Liang, Shu-Hsin Chang, Chung-Lun Huang, You-Yu Nian, Zhe Wan, Sushil Kumar, Cheng-Xin Xue, Gajanan Jedhe, Hidehiro Fujiwara, Haruki Mori, Chih-Wei Chen, Po-Hua Huang, Chih-Feng Juan, Chung-Yi Chen, Tsung-Yao Lin, Ch Wang, Chih-Cheng Chen, Kevin Jou
    MediaTek · TSMC
  58. ISSCC
    2024
    3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from −25°C to 125°C
    DOI
    Bei-Shing Lien, Szu Lin Liu, Wei-Lin Lai, Yi-Chen Lu, Yung-Chow Peng, Kenny Cheng-Hsiang Hsieh
    TSMC
  59. ISSCC
    2024
    30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
    DOI
    Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC · Daegu Gyeongbuk Institute of Science and Technology
  60. ISSCC
    2024
    34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices
    DOI
    Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    TSMC · National Tsing Hua University · Industrial Technology Research Institute
  61. ISSCC
    2024
    34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell
    DOI
    Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  62. ISSCC
    2024
    34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices
    DOI
    Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  63. JSSC
    2024
    A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality
    DOI
    Wen-Cong Huang, I-Ting Lin, Ying-Sheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · MediaTek · University of California, Berkeley · TSMC
  64. JSSC
    2024
    A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices
    DOI
    Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · MediaTek · TSMC
  65. JSSC
    2024
    A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  66. JSSC
    2024
    A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking
    DOI
    Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC
  67. JSSC
    2024
    A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme
    DOI
    Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  68. JSSC
    2024
    An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices
    DOI
    De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chi-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  69. JSSC
    2024
    EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
    DOI
    Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina
    Stanford University · TSMC
  70. VLSI
    2024
    A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4
    DOI
    Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, C.H. Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee
    TSMC
  71. VLSI
    2024
    A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro
    DOI
    De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  72. VLSI
    2024
    A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications
    DOI
    Ming-Chieh Huang, Wei Wing Mar, Shankar Kanade, Boris Bai, Aditya Gayatri, Krishna Khairnar, Amy Lai, Yu-Hao Hsu, Hung-Jen Liao, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC
  73. VLSI
    2024
    A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  74. VLSI
    2024
    An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology
    DOI
    Tsung-Che Lu, Chin-Ming Fu, Wei-Hsiang Wang, Fred Kuo, Chih-Hsien Chang, Kenny Hsieh, King-Ho Tam, Tze-Chiang Huang, Tom Chen, Mei Wong, Wei-Pin Changchien, Frank Lee
    TSMC
  75. VLSI
    2024
    Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process
    DOI
    Chu-En Hsia, Chin-Ho Chang, Yung-Shun Chen, Po-Yu Lai, Ching Lin Jen, Yung-Chow Peng, Shenggao Li
    TSMC
  76. VLSI
    2024
    MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating
    DOI
    Kartik Prabhu, Robert M. Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC
  77. ESSERC
    2023
    EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry
    DOI
    Luke R. Upton, Akash Levy, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann
    Stanford University · TSMC
  78. ISSCC
    2023
    2.5 A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots
    DOI
    I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · TSMC
  79. ISSCC
    2023
    33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity
    DOI
    Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
    TSMC
  80. ISSCC
    2023
    A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices
    DOI
    Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  81. ISSCC
    2023
    A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow
    DOI
    Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · Delta Electronics (Taiwan) · TSMC
  82. ISSCC
    2023
    A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
    DOI
    Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC（日本拠点）TSMC Japan · TSMC
  83. ISSCC
    2023
    A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking
    DOI
    Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC
  84. ISSCC
    2023
    A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing
    DOI
    Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
    National Taiwan University · National Yang Ming Chiao Tung University · TSMC
  85. ISSCC
    2023
    A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W
    DOI
    Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Huna-Hsi Hsu, Yu-Hsiana Chin, Yu-Chiao Chen, Chuna-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  86. JSSC
    2023
    8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices
    DOI
    Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  87. VLSI
    2023
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  88. VLSI
    2023
    A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation
    DOI
    Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin S. Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC
  89. VLSI
    2023
    A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices
    DOI
    Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC · National Chung Hsing University
  90. VLSI
    2023
    A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  91. VLSI
    2023
    A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications
    DOI
    Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li
    TSMC
  92. VLSI
    2023
    A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology
    DOI
    Nick Zhang, Young Suk Kim, Peter Hsu, Samsoo Kim, Derek Tao, Hung-Jen Liao, P.W. Wang, Geoffrey Yeap, Quincy Li, Tsung-Yung Jonathan Chang
    TSMC
  93. VLSI
    2023
    How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology
    DOI
    H.-L. Chiang, R. A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Y.-H. Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, M.-H. Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, C. Enz, M.-C. F. Chang, M.-F. Chang, H.-S. P. Wong, I. P. Radu
    TSMC · University of California, Los Angeles · École Polytechnique Fédérale de Lausanne · National Cheng Kung University
  94. VLSI
    2023
    Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs
    DOI
    Wei-Xiang You, Cheng-Yin Wang, Yih Wang, Tsung-Yung Jonathan Chang, Szuya Sandy Liao
    TSMC
  95. A-SSCC
    2022
    A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AI
    DOI
    Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · TSMC
  96. CICC
    2022
    Interconnect in the Era of 3DIC
    DOI
    Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai
    TSMC
  97. ISSCC
    2022
    A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations
    DOI
    Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsin Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung, Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  98. ISSCC
    2022
    A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices
    DOI
    Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang
    TSMC · National Tsing Hua University
  99. ISSCC
    2022
    A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems
    DOI
    Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC
  100. ISSCC
    2022
    A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range
    DOI
    Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC
  101. ISSCC
    2022
    A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations
    DOI
    Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  102. ISSCC
    2022
    A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
    DOI
    Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski
    TSMC · University College Dublin
  103. ISSCC
    2022
    An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices
    DOI
    Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC
  104. JSSC
    2022
    A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device
    DOI
    Yen-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng-Fan Chang
    National Tsing Hua University · TSMC · University of Florida
  105. JSSC
    2022
    A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding
    DOI
    Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · Daegu Gyeongbuk Institute of Science and Technology · TSMC
  106. JSSC
    2022
    A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection
    DOI
    Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · Daegu Gyeongbuk Institute of Science and Technology · TSMC
  107. JSSC
    2022
    CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference
    DOI
    Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guenole Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina
    Stanford University · TSMC · Meta
  108. VLSI
    2022
    A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications
    DOI
    Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang
    TSMC
  109. VLSI
    2022
    A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology
    DOI
    Nail Etkin Can Akkaya, Gary Chan, H.J. Liao, Yih Wang, Jonathan Chang
    TSMC · TSMC
  110. VLSI
    2022
    A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality
    DOI
    Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang
    National Taiwan University · TSMC
  111. VLSI
    2022
    Semiconductor Innovations, from Device to System
    DOI
    Yuh-Jier Mii
    TSMC