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企業・研究機関Company / Institute · アメリカUSA · 2022–2026 LIVE

TSMC

アメリカUSA 9位 (18 pt) · 世界World 28位 (0 pt) · 対象論文Papers 19

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

024682022 ISSCC: 12022 VLSI: 12022 JSSC: 1320222023 ISSCC: 1120232024 ISSCC: 1120242025 ISSCC: 32025 VLSI: 12025 JSSC: 12025 A-SSCC: 1620252026 ISSCC: 32026 VLSI: 12026 JSSC: 482026
ISSCCVLSIJSSCA-SSCC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC11133
VLSI1––11
JSSC1––14
A-SSCC–––1–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1900.71アメリカUSA #5 · 世界World #12
VLSI Tier 1310.61アメリカUSA #8 · 世界World #19
JSSC Tier 1600.87アメリカUSA #12 · 世界World #32
CICC Tier 2000.00–
A-SSCC Tier 2100.09アメリカUSA #6 · 世界World #25
ESSERC Tier 2000.00–

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. ISSCC
    2026
    30.5 A 16nm 72kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks
    DOI
    Jen-Chun Tien, Win-San Khwa, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Yu-Sheng Kao, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, De-Qi You, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  2. ISSCC
    2026
    8.2 A 32Gb/s 12.35Tb/s/mm 2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging
    DOI
    Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh
    TSMC · TSMC
  3. ISSCC
    2026
    A 22nm 96Mb 50.6-to-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN
    DOI
    Hung-Hsi Hsu, Win-San Khwa, Yao-Kai Yeh, Chih-Ling Wu, Chang-Yuan Chen, Yen-Che Huang, Yen-Hua Lin, Cheng-Feng Chang, Yen-Tung Shao, Jen-Chun Tien, De-Qi You, Ping-Sheng Wu, Bo Zhang, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  4. JSSC
    2026
    A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time
    DOI
    Haris Suhail, Haoran He, Vinod Kurian Jacob, Jiyue Yang, Kang L. Wang, Sudhakar Pamarti
    NVIDIA · TSMC · University of California, Los Angeles
  5. JSSC
    2026
    A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
    DOI
    Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  6. JSSC
    2026
    A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models
    DOI
    Che-Kai Liu, Zishen Wan, Young-Seok Noh, Mohamed Ibrahim, Samuel D. Spetalnick, Tushar Krishna, Win-San Khwa, Ashwin Sanjay Lele, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
    Georgia Institute of Technology · TSMC · TSMC
  7. JSSC
    2026
    A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  8. VLSI
    2026
    A 2nm 234.4 TOPS/W and 511.9 $\text{TOPS}/\text{mm}^{2}$ Digital Computing-in-Memory Compiler with Multiple MAC Units per Weight and Multiple Data Format Support
    DOI
    Hidehiro Fujiwara, Brian Crafton, Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Ashwin Sanjay LeLe, Bo Zhang, Chao-Kai Chuang, Hiroaki Ishii, Cheng-En Lee, Vineet Joshi, Xiaochen Peng, Xiaoyu Sun, Shu-Huan Hsu, Yao-Yi Liu, Takeshi Hashizume, Yu-Hao Hsu, Win-San Khwa, Saman Adham, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Kerem Akarvardar, Meng-Fan Chang, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  9. A-SSCC
    2025
    CENTAUR: A 38.5-TFLOPS/W 600MHz Floating-Point Digital Compute-In-Memory Engine with 40nm Fusion RRAM-eDRAM Macros Featuring 3D-MAC Operation
    DOI
    Luqi Zheng, Amir Massah Bavani, Shuting Du, Te-Yu Hsin, Mufeng Chen, Win-San Khwa, Ashwin Lele, Harry Chuang, Yu-Der Chih, Meng-Fan Chang, Haitong Li
    Purdue University West Lafayette · TSMC · TSMC
  10. ISSCC
    2025
    14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks
    DOI
    De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · TSMC
  11. ISSCC
    2025
    14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices
    DOI
    Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
    TSMC · National Tsing Hua University · TSMC
  12. ISSCC
    2025
    36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating
    DOI
    Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan Drake, Chin-Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem
    TSMC · TSMC · TSMC · AMD
  13. JSSC
    2025
    A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device
    DOI
    Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
    National Tsing Hua University · TSMC · Georgia Institute of Technology · TSMC
  14. VLSI
    2025
    A 3nm 125 Tops/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8 and FP16 Digital-CIM Compiler with Multi-Weight Update/Cycle
    DOI
    Haruki Mori, J-M. Hung, W-C. Zhao, K. Khare, B. Crafton, H. Ishii, C-E. Lee, X. Peng, X. Sun, Y. Fujino, C-J. Tsen, V. Joshi, C-K. Chuang, T. Hashizume, C-F. Lee, T-L. Chou, K. Akarvardar, S. Adham, Y. Wang, H. Fujiwara, Y-D. Chih, Y-H. Chen, H-J. Liao, T-Y. Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  15. ISSCC
    2024
    34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell
    DOI
    Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  16. ISSCC
    2023
    A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
    DOI
    Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC（日本拠点）TSMC Japan · TSMC
  17. ISSCC
    2022
    A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations
    DOI
    Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  18. JSSC
    2022
    A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
    DOI
    Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu
    Georgia Institute of Technology · TSMC
  19. VLSI
    2022
    A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology
    DOI
    Nail Etkin Can Akkaya, Gary Chan, H.J. Liao, Yih Wang, Jonathan Chang
    TSMC · TSMC