JSSC · 2022–2026 LIVE

TSMC

対象論文Papers 6 · 筆頭著者first author 0 · 著者按分fractional 0.87 · アメリカUSA #12 · 世界World #32

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Ashwin Sanjay Lele ORCID	2
1	Bo Zhang	2
1	Xiaoyu Sun ORCID	2
4	Brian Crafton ORCID	1
4	Haoran He	1
4	Kerem Akarvardar ORCID	1
4	Saman Adham	1
4	Vineet Joshi	1
4	Xiaochen Peng	1

対象論文Papers

JSSC
2026

A 180-nm Voltage-Controlled Magneto-Electric RAM With Sub-1-ns Switching Time
DOI
Haris Suhail, Haoran He, Vinod Kurian Jacob, Jiyue Yang, Kang L. Wang, Sudhakar Pamarti

NVIDIA · TSMC · University of California, Los Angeles
JSSC
2026

A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
DOI
Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang

TSMC · TSMC · TSMC（日本拠点）TSMC Japan
JSSC
2026

A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models
DOI
Che-Kai Liu, Zishen Wan, Young-Seok Noh, Mohamed Ibrahim, Samuel D. Spetalnick, Tushar Krishna, Win-San Khwa, Ashwin Sanjay Lele, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury

Georgia Institute of Technology · TSMC · TSMC
JSSC
2026

A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks
DOI
De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

National Tsing Hua University · TSMC · TSMC
JSSC
2025

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device
DOI
Hung-Hsi Hsu, Tai-Hao Wen, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Ashwin Sanjay Lele, Bo Zhang, Ping-Sheng Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

National Tsing Hua University · TSMC · Georgia Institute of Technology · TSMC
JSSC
2022

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
DOI
Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu

Georgia Institute of Technology · TSMC