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JSSC · 2022–2026 LIVE

TSMC（日本拠点）TSMC Japan

対象論文Papers 7 · 筆頭著者first author 6 · 著者按分fractional 2.91 · 日本Japan #1 · 世界World #25

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Koji Nii ORCID6
2Yumito Aoyagi ORCID4
3Makoto Yabuuchi ORCID3
3Tomotaka Tanaka ORCID3
3Yuichiro Ishii3
6Kazuto Mizutani2
6Masaya Hamada2
6Takaaki Nakazato2
6Yorinobu Fujino2
6Yoshiaki Osada ORCID2
11Hidemitsu Kojima ORCID1
11Hiroaki Ishii ORCID1
11Hiromasa Otsubo1
11Kazumasa Uno1
11Masaru Haraguchi ORCID1
11Ryota Watanabe ORCID1
11Takeshi Hashizume1
11Yoshisato Yokoyama ORCID1

対象論文Papers

  1. JSSC
    2026
    A 13.8% Speed-Enhanced 1 T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Koji Nii, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  2. JSSC
    2026
    A 3 nm Fin-FET 19.87-Mbit/mm 2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  3. JSSC
    2026
    A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
    DOI
    Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  4. JSSC
    2026
    A 3-nm FinFET 563-kbit 35.5-Mbit/mm 2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  5. JSSC
    2025
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  6. JSSC
    2025
    A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
    DOI
    Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  7. JSSC
    2024
    A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC