TopSSCS
← 総合ランキングへ戻るBack to overall ranking

企業・研究機関Company / Institute · 日本Japan · 2022–2026 LIVE

TSMC（日本拠点）TSMC Japan

TSMC Japan

日本Japan 1位 (70.5 pt) · 世界World 19位 (4 pt) · 対象論文Papers 23

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

024682022 ISSCC: 1120222023 ISSCC: 12023 VLSI: 2320232024 ISSCC: 22024 VLSI: 12024 JSSC: 12024 ESSERC: 1520242025 ISSCC: 12025 VLSI: 42025 JSSC: 2720252026 VLSI: 32026 JSSC: 472026
ISSCCVLSIJSSCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC1121–
VLSI–2143
JSSC––124
ESSERC––1––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1510.84日本Japan #3 · 世界World #25
VLSI Tier 11084.44日本Japan #2 · 世界World #8
JSSC Tier 1762.91日本Japan #1 · 世界World #25
CICC Tier 2000.00–
A-SSCC Tier 2000.00–
ESSERC Tier 2110.25日本Japan #1 · 世界World #41

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. JSSC
    2026
    A 13.8% Speed-Enhanced 1 T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Koji Nii, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  2. JSSC
    2026
    A 3 nm Fin-FET 19.87-Mbit/mm 2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  3. JSSC
    2026
    A 3 nm FinFET 125 TOPS/W-29 TFLOPS/W, 90 TOPS/mm 2 -17 TFLOPS/mm 2 SRAM-Based INT8, and FP16 Digital-CIM Compiler With Support for Multi-Weight Update/Cycle
    DOI
    Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Kinshuk Khare, Brian Crafton, Hiroaki Ishii, Cheng-En Lee, Xiaochen Peng, Xiaoyu Sun, Yorinobu Fujino, Chia-Jung Tsen, Vineet Joshi, Chao-Kai Chuang, Takeshi Hashizume, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Hidehiro Fujiwara, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  4. JSSC
    2026
    A 3-nm FinFET 563-kbit 35.5-Mbit/mm 2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  5. VLSI
    2026
    A $\mathbf{2 n m}$ 37.4 Mbit $/ \text{mm}^{2}$ Dual-Rail SRAM with Row-Access Aware Read Tracking and Write Assist Circuits Enabling 2.28 pJ/Access Energy Efficient Operation
    DOI
    Ryo Takamatsu, Makoto Yabuuchi, Masaya Hamada, Tomotaka Tanaka, Shu-Huan Hsu, Yao-Yi Liu, Yuichiro Ishii, Koji Nii, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  6. VLSI
    2026
    A 25.3% Area-Efficient 1CPP Mask ROM with Robust Power Mesh on 2-nm NanoSheet Logic CMOS
    DOI
    Ryota Watanabe, Kazumasa Uno, Hidemitsu Kojima, Ayumu Yamada, Hiromasa Otsubo, Ted Chu, Tsung-Hsien Huang, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  7. VLSI
    2026
    A 2nm 234.4 TOPS/W and 511.9 $\text{TOPS}/\text{mm}^{2}$ Digital Computing-in-Memory Compiler with Multiple MAC Units per Weight and Multiple Data Format Support
    DOI
    Hidehiro Fujiwara, Brian Crafton, Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Ashwin Sanjay LeLe, Bo Zhang, Chao-Kai Chuang, Hiroaki Ishii, Cheng-En Lee, Vineet Joshi, Xiaochen Peng, Xiaoyu Sun, Shu-Huan Hsu, Yao-Yi Liu, Takeshi Hashizume, Yu-Hao Hsu, Win-San Khwa, Saman Adham, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Kerem Akarvardar, Meng-Fan Chang, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  8. ISSCC
    2025
    29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme
    DOI
    Hidehiro Fujiwara, Wei-Chang Zhao, Kinshuk Khare, Yi-Hsin Nien, Chih-Yu Lin, Cheng-Han Lin, Shan-Ru Liao, Kenta Torigoe, Shirleen Xia, Yuichiro Ishii, Yao-Yi Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC（日本拠点）TSMC Japan
  9. JSSC
    2025
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  10. JSSC
    2025
    A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
    DOI
    Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  11. VLSI
    2025
    A 13.8% Speed-Enhanced 1T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  12. VLSI
    2025
    A 3nm 125 Tops/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8 and FP16 Digital-CIM Compiler with Multi-Weight Update/Cycle
    DOI
    Haruki Mori, J-M. Hung, W-C. Zhao, K. Khare, B. Crafton, H. Ishii, C-E. Lee, X. Peng, X. Sun, Y. Fujino, C-J. Tsen, V. Joshi, C-K. Chuang, T. Hashizume, C-F. Lee, T-L. Chou, K. Akarvardar, S. Adham, Y. Wang, H. Fujiwara, Y-D. Chih, Y-H. Chen, H-J. Liao, T-Y. Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  13. VLSI
    2025
    A 3nm FinFET 563kbit 35.5Mbit/mm2 Dual-Rail SRAM with 3.89pJ/Access High Energy Efficient andμW/Mbit 1-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Koji Nii, Mark Zhou, J.C. Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  14. VLSI
    2025
    A Prototype 16Mbit RRAM on 55nm BCD with 56% Compact-Area Wordline Driver and Constant Write-Current Scheme for Automotive 150°C Operation
    DOI
    Kohei Santo, Masayoshi Nakayama, Reiji Mochida, Hitoshi Suwa, Motoki Tamura, Atsuo Mangyo, Koji Nii, Yu-Cheng Lin, C.F. Wang, Wu-Chin Tsai, Y.D. Chih, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  15. ESSERC
    2024
    A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC
    DOI
    Kota Shiba, Zhijie Zhan, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    TSMC（日本拠点）TSMC Japan · 東京大学The University of Tokyo · TSMC
  16. ISSCC
    2024
    15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture
    DOI
    Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  17. ISSCC
    2024
    34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell
    DOI
    Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  18. JSSC
    2024
    A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  19. VLSI
    2024
    A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  20. ISSCC
    2023
    A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
    DOI
    Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC（日本拠点）TSMC Japan · TSMC
  21. VLSI
    2023
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  22. VLSI
    2023
    A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  23. ISSCC
    2022
    A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations
    DOI
    Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan