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VLSI · 2022–2026 LIVE

TSMC（日本拠点）TSMC Japan

対象論文Papers 10 · 筆頭著者first author 8 · 著者按分fractional 4.44 · 日本Japan #2 · 世界World #8

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Koji Nii ORCID8
2Makoto Yabuuchi ORCID4
2Tomotaka Tanaka ORCID4
2Yuichiro Ishii4
5Masaya Hamada3
5Yumito Aoyagi ORCID3
7Hidemitsu Kojima ORCID2
7Hiromasa Otsubo2
7Kazumasa Uno2
7Kazuto Mizutani2
7Ryota Watanabe ORCID2
7Takaaki Nakazato2
7Yoshiaki Osada ORCID2
14Atsuo Mangyo1
14Ayumu Yamada1
14H. Ishii1
14Hiroaki Ishii ORCID1
14Hitoshi Suwa1
14Kohei Santo1
14Masayoshi Nakayama1
14Motoki Tamura1
14Reiji Mochida1
14Ryo Takamatsu1
14T. Hashizume1
14Takeshi Hashizume1
14Y. Fujino1
14Yih Wang1

対象論文Papers

  1. VLSI
    2026
    A $\mathbf{2 n m}$ 37.4 Mbit $/ \text{mm}^{2}$ Dual-Rail SRAM with Row-Access Aware Read Tracking and Write Assist Circuits Enabling 2.28 pJ/Access Energy Efficient Operation
    DOI
    Ryo Takamatsu, Makoto Yabuuchi, Masaya Hamada, Tomotaka Tanaka, Shu-Huan Hsu, Yao-Yi Liu, Yuichiro Ishii, Koji Nii, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  2. VLSI
    2026
    A 25.3% Area-Efficient 1CPP Mask ROM with Robust Power Mesh on 2-nm NanoSheet Logic CMOS
    DOI
    Ryota Watanabe, Kazumasa Uno, Hidemitsu Kojima, Ayumu Yamada, Hiromasa Otsubo, Ted Chu, Tsung-Hsien Huang, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  3. VLSI
    2026
    A 2nm 234.4 TOPS/W and 511.9 $\text{TOPS}/\text{mm}^{2}$ Digital Computing-in-Memory Compiler with Multiple MAC Units per Weight and Multiple Data Format Support
    DOI
    Hidehiro Fujiwara, Brian Crafton, Haruki Mori, Je-Min Hung, Wei-Chang Zhao, Ashwin Sanjay LeLe, Bo Zhang, Chao-Kai Chuang, Hiroaki Ishii, Cheng-En Lee, Vineet Joshi, Xiaochen Peng, Xiaoyu Sun, Shu-Huan Hsu, Yao-Yi Liu, Takeshi Hashizume, Yu-Hao Hsu, Win-San Khwa, Saman Adham, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Kerem Akarvardar, Meng-Fan Chang, Tsung-Yung Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  4. VLSI
    2025
    A 13.8% Speed-Enhanced 1T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS
    DOI
    Ryota Watanabe, Hidemitsu Kojima, Kazumasa Uno, Hiromasa Otsubo, Ted Chu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  5. VLSI
    2025
    A 3nm 125 Tops/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8 and FP16 Digital-CIM Compiler with Multi-Weight Update/Cycle
    DOI
    Haruki Mori, J-M. Hung, W-C. Zhao, K. Khare, B. Crafton, H. Ishii, C-E. Lee, X. Peng, X. Sun, Y. Fujino, C-J. Tsen, V. Joshi, C-K. Chuang, T. Hashizume, C-F. Lee, T-L. Chou, K. Akarvardar, S. Adham, Y. Wang, H. Fujiwara, Y-D. Chih, Y-H. Chen, H-J. Liao, T-Y. Jonathan Chang
    TSMC · TSMC · TSMC（日本拠点）TSMC Japan
  6. VLSI
    2025
    A 3nm FinFET 563kbit 35.5Mbit/mm2 Dual-Rail SRAM with 3.89pJ/Access High Energy Efficient andμW/Mbit 1-Cycle Latency Low-Leakage Mode
    DOI
    Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Koji Nii, Mark Zhou, J.C. Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  7. VLSI
    2025
    A Prototype 16Mbit RRAM on 55nm BCD with 56% Compact-Area Wordline Driver and Constant Write-Current Scheme for Automotive 150°C Operation
    DOI
    Kohei Santo, Masayoshi Nakayama, Reiji Mochida, Hitoshi Suwa, Motoki Tamura, Atsuo Mangyo, Koji Nii, Yu-Cheng Lin, C.F. Wang, Wu-Chin Tsai, Y.D. Chih, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  8. VLSI
    2024
    A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction
    DOI
    Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  9. VLSI
    2023
    3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications
    DOI
    Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC
  10. VLSI
    2023
    A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking
    DOI
    Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
    TSMC（日本拠点）TSMC Japan · TSMC