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JSSC · 2022–2026 LIVE

University College Dublin

対象論文Papers 27 · 筆頭著者first author 16 · 著者按分fractional 14.93 · 世界World #26

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Robert Bogdan Staszewski ORCID22
2Teerachot Siriburanon ORCID9
3Anding Zhu ORCID7
4Jianglin Du ORCID4
5Sayan Kumar ORCID3
5Xi Chen ORCID3
5Yizhe Hu ORCID3
8Amir Bozorg ORCID2
8Feifan Hong ORCID2
8Jiawen Chen ORCID2
8Michael Peter Kennedy ORCID2
8Patchara Sawakewang2
8Viet Nguyen ORCID2
14Chawin Khongprasongsiri ORCID1
14Chenhao Chu ORCID1
14Chunxiao Liu ORCID1
14Dawei Mai ORCID1
14Enis Kobal ORCID1
14Filippo Schembari ORCID1
14Haoyang Jia ORCID1
14Hieu Minh Nguyen ORCID1
14Jingzhou Pang ORCID1
14Lin Qi ORCID1
14Luca Avallone ORCID1
14Peng Chen ORCID1
14Pingda Guan ORCID1
14Ruijia Liu ORCID1
14Sumit Dash1
14Vivek Govindaraj1
14Yevhenii Mormul ORCID1

対象論文Papers

  1. JSSC
    2026
    A 0.5--2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping
    DOI
    Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University of Macau · University College Dublin
  2. JSSC
    2026
    A 24.5–45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation
    DOI
    Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  3. JSSC
    2026
    A 24–28-GHz Single-Chip GaN MMIC T/R Front-End Using Doherty Power Amplifier as Embedded Switches in Rx Mode
    DOI
    Ruijia Liu, Haoyang Jia, Lin Qi, Anding Zhu
    University College Dublin
  4. JSSC
    2026
    A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter
    DOI
    Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  5. JSSC
    2026
    A PLL Technique: Charge-Steering Sampling
    DOI
    Weichen Tao, Yuhao Yang, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  6. JSSC
    2026
    A Pseudo-Series Resonance CMOS Oscillator
    DOI
    Jiawen Chen, Kai Xu, Teerachot Siriburanon, Robert Bogdan Staszewski
    University College Dublin · King's College London
  7. JSSC
    2026
    A SAR Time-to-Digital Converter Embedding Time-Domain Noise-Shaping Self-Calibration
    DOI
    Yevhenii Mormul, Viet Nguyen, Robert Bogdan Staszewski
    University College Dublin
  8. JSSC
    2025
    A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique
    DOI
    Xiangjian Kong, Kai Xu, Huanlin Xie, Mingchao Jian, Hao Lian, Robert Bogdan Staszewski, Chunbing Guo
    Guangdong University of Technology · King's College London · University College Dublin
  9. JSSC
    2025
    A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling
    DOI
    Weichen Tao, Yuhao Yang, Weiyi Chen, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  10. JSSC
    2025
    A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator
    DOI
    Teerachot Siriburanon, Xi Chen, Chunxiao Liu, Jianglin Du, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin
  11. JSSC
    2025
    A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations
    DOI
    Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski
    University College Dublin · MediaTek
  12. JSSC
    2024
    A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces
    DOI
    Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi
    Tsinghua University · University College Dublin
  13. JSSC
    2024
    A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS
    DOI
    Chenyu Xu, Xiaofei Liao, Mengru Yang, Feifan Hong, Peijuan Ju, Wendi Chen, Pengfei Diao, Hao Gong, Xiang Liu, Xiaohu You, Dixian Zhao
    Purple Mountain Laboratories · Southeast University · University College Dublin
  14. JSSC
    2024
    Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop
    DOI
    Zhong Gao, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · University College Dublin
  15. JSSC
    2023
    A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness
    DOI
    Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
    University College Dublin · University of Science and Technology of China
  16. JSSC
    2023
    A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion
    DOI
    Zhong Gao, Martin Fritz, Gerd Spalink, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · University College Dublin
  17. JSSC
    2023
    A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit
    DOI
    Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · NXP · Hong Kong University of Science and Technology · The Hong Kong University of Science and Technology (Guangzhou) · University College Dublin
  18. JSSC
    2022
    A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
    DOI
    Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Qualcomm · Infineon · University College Dublin
  19. JSSC
    2022
    A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection
    DOI
    Amir Bozorg, Robert Bogdan Staszewski
    University College Dublin
  20. JSSC
    2022
    A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking
    DOI
    Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin
  21. JSSC
    2022
    A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters
    DOI
    Amir Bozorg, Robert Bogdan Staszewski
    University College Dublin
  22. JSSC
    2022
    A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range
    DOI
    Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin
  23. JSSC
    2022
    A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC
    DOI
    Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski
    University College Dublin
  24. JSSC
    2022
    A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple
    DOI
    Yue Chen, Jiang Gong, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · University College Dublin
  25. JSSC
    2022
    A mm-Wave Switched-Capacitor RFDAC
    DOI
    Hieu Minh Nguyen, Jeffrey Sean Walling, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin · Virginia Tech
  26. JSSC
    2022
    Broadband GaN MMIC Doherty Power Amplifier Using Continuous-Mode Combining for 5G Sub-6 GHz Applications
    DOI
    Jingzhou Pang, Chenhao Chu, Jiayan Wu, Zhijiang Dai, Mingyu Li, Songbai He, Anding Zhu
    University College Dublin · Chongqing University · University of Electronic Science and Technology of China
  27. JSSC
    2022
    Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer
    DOI
    Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Mike Keaveney
    University College Dublin · Analog Devices · Limerick Institute of Technology