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大学University · IE · 2022–2026 LIVE

University College Dublin

世界World 25位 (0 pt) · 対象論文Papers 51

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

0510152022 ISSCC: 22022 VLSI: 12022 JSSC: 101320222023 VLSI: 22023 JSSC: 32023 CICC: 1620232024 ISSCC: 12024 VLSI: 22024 JSSC: 32024 A-SSCC: 12024 ESSERC: 1820242025 ISSCC: 12025 VLSI: 42025 JSSC: 42025 CICC: 12025 A-SSCC: 12025 ESSERC: 31420252026 ISSCC: 12026 VLSI: 12026 JSSC: 72026 CICC: 1102026
ISSCCVLSIJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC2–111
VLSI12241
JSSC103347
CICC–1–11
A-SSCC––11–
ESSERC––13–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1531.94世界World #60
VLSI Tier 11055.72世界World #20
JSSC Tier 1271614.93世界World #26
CICC Tier 2321.62世界World #65
A-SSCC Tier 2211.11世界World #53
ESSERC Tier 2422.08世界World #42

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A Class-F 23 Magnetic-Coupled 8-Phase Oscillator Employing Rotational Quadrifilar Winding
    DOI
    Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  2. ISSCC
    2026
    27.9 A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock
    DOI
    Jiawen Chen, Kai Xu, Luyi Guo, Teerachot Siriburanon, Jun Yin, Bashir M. Al-Hashimi, Robert Bogdan Staszewski
    University College Dublin · King's College London · University of Macau
  3. JSSC
    2026
    A 0.5--2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping
    DOI
    Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University of Macau · University College Dublin
  4. JSSC
    2026
    A 24.5–45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation
    DOI
    Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  5. JSSC
    2026
    A 24–28-GHz Single-Chip GaN MMIC T/R Front-End Using Doherty Power Amplifier as Embedded Switches in Rx Mode
    DOI
    Ruijia Liu, Haoyang Jia, Lin Qi, Anding Zhu
    University College Dublin
  6. JSSC
    2026
    A 31.5–36-GHz Low-Spur Digitally Assisted Gain-Boosting Charge-Sharing Locking PLL Achieving 54-fs RMS Jitter
    DOI
    Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  7. JSSC
    2026
    A PLL Technique: Charge-Steering Sampling
    DOI
    Weichen Tao, Yuhao Yang, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  8. JSSC
    2026
    A Pseudo-Series Resonance CMOS Oscillator
    DOI
    Jiawen Chen, Kai Xu, Teerachot Siriburanon, Robert Bogdan Staszewski
    University College Dublin · King's College London
  9. JSSC
    2026
    A SAR Time-to-Digital Converter Embedding Time-Domain Noise-Shaping Self-Calibration
    DOI
    Yevhenii Mormul, Viet Nguyen, Robert Bogdan Staszewski
    University College Dublin
  10. VLSI
    2026
    A 28-GHz Quadrature LO-Phase-Shifting Digital Wave-Locked Loop (WLL) Achieving 57.2-fs rms Jitter, -80.6-dBc Spur ref , and 0.59-μs Near-Integer Lock Time
    DOI
    Feifan Hong, Jiawen Chen, Chunxiao Liu, Pingda Guan, Robert B. Staszewski, Teerachot Siriburanon
    University College Dublin
  11. A-SSCC
    2025
    A 25.48-29.25 GHz Rotary Traveling-Wave Oscillator Achieving -191dBc/Hz FoM at 10 MHz Offset Using RingInterleaved N/P Cross-Coupled Pairs in 22-nm CMOS
    DOI
    Junlin Li, Juncheng Deng, Zhongjun Zhang, Jing Liu, Zhongguang Xu, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  12. CICC
    2025
    A 0.0022 mm2, 2 GS/s Resettable VCO-Based ADC With-out Quantization Noise Shaping
    DOI
    Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Robert Bogdan Staszewski, Fujiang Lin, Liheng Lou, Yizhe Hu
    University of Science and Technology of China · University of Macau · University College Dublin
  13. ESSERC
    2025
    A $25-31-\text{GHz} 0.98-\text{mW}$ Dual-Ellipse Vector-Summing Variable-Gain Phase Shifter With Current-Reusing Enabling Calibration-Free Orthogonal Phase and Gain Control
    DOI
    Zhe Zhang, Pingda Guan, Apisak Worapishet, Wei Deng, R. Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin · Mahanakorn University of Technology · Tsinghua University
  14. ESSERC
    2025
    A 9-B 35 TOPS/W Differential Ring-Oscillator Based Multiply-And-Accumulate Macro with On-Chip PVT Calibration
    DOI
    Chawin Khongprasongsiri, Sayan Kumar, Fergal Kilgannon, Derek Shaw, Panassaya Ounsawatdipong, Teerachot Siriburanon, Robert Bogdan Staszewski
    University College Dublin
  15. ESSERC
    2025
    Passive Techniques to Reduce Supply Sensitivity in an LC Oscillator Achieving 46-dB Suppression
    DOI
    Renxu Yang, Robert Bogdan Staszewski, Masoud Babaie, Zhirui Zong
    The Hong Kong University of Science and Technology (Guangzhou) · University College Dublin · Delft University of Technology
  16. ISSCC
    2025
    19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz
    DOI
    Jiawen Chen, Kai Xu, Teerachot Siriburanon, Robert Bogdan Staszewski
    University College Dublin · King's College London
  17. JSSC
    2025
    A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique
    DOI
    Xiangjian Kong, Kai Xu, Huanlin Xie, Mingchao Jian, Hao Lian, Robert Bogdan Staszewski, Chunbing Guo
    Guangdong University of Technology · King's College London · University College Dublin
  18. JSSC
    2025
    A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling
    DOI
    Weichen Tao, Yuhao Yang, Weiyi Chen, Robert Bogdan Staszewski, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  19. JSSC
    2025
    A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator
    DOI
    Teerachot Siriburanon, Xi Chen, Chunxiao Liu, Jianglin Du, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin
  20. JSSC
    2025
    A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations
    DOI
    Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski
    University College Dublin · MediaTek
  21. VLSI
    2025
    A 0.184mm 2 $W$-Band Single-RTWO-Based Subharmonic RX Achieving 3.72 dB-NF and I/Q Mismatch < 0.8° in 22 nm CMOS
    DOI
    Juncheng Deng, Aodi Li, Junlin Li, Weichen Tao, Shaoqi Yang, Zhongjun Zhang, Yuhao Yang, Xin Cheng, Fujiang Lin, Robert Bogdan Staszewski, Liheng Lou, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  22. VLSI
    2025
    A 24.5-to-45.2-GHz Dual-Injection Clock Multiplier with Folded-Inductor-Based Magnetic-Flux Cancellation Achieving 32.83-fsrms Jitter and 0.037-mm2 Core Area
    DOI
    Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert B. Staszewski, Teerachot Siriburanon
    University College Dublin
  23. VLSI
    2025
    A 31.5-36 GHz Low-Spur Gain-Boosting Charge-Sharing Locking PLL with 54fs Jitter
    DOI
    Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  24. VLSI
    2025
    A Pipelined-SAR-TDC with Time-Domain Noise-Shaping Self-Calibration
    DOI
    Yevhenii Mormul, Viet Nguyen, Robert Bogdan Staszewski
    University College Dublin
  25. A-SSCC
    2024
    A Tiny 3.15–43.4-GHz 3.6-mW Divide-by-8 Ring-Based Injection-Locked Frequency Divider Using Multiphase Waveform Gating Technique
    DOI
    Feifan Hong, Xi Chen, Anding Zhu, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  26. ESSERC
    2024
    A Compact 21-25 GHz Charge-Domain Fractional-N ADPLL with 168 fs Total RMS Jitter
    DOI
    Weichen Tao, Yongheng Liu, Yuhao Yang, R. Bogdan Staszewski, Fujiang Lin, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  27. ISSCC
    2024
    10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs
    DOI
    Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin
    University College Dublin · Analog Devices
  28. JSSC
    2024
    A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces
    DOI
    Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi
    Tsinghua University · University College Dublin
  29. JSSC
    2024
    A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS
    DOI
    Chenyu Xu, Xiaofei Liao, Mengru Yang, Feifan Hong, Peijuan Ju, Wendi Chen, Pengfei Diao, Hao Gong, Xiang Liu, Xiaohu You, Dixian Zhao
    Purple Mountain Laboratories · Southeast University · University College Dublin
  30. JSSC
    2024
    Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop
    DOI
    Zhong Gao, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · University College Dublin
  31. VLSI
    2024
    A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling
    DOI
    Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski
    University College Dublin
  32. VLSI
    2024
    A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement
    DOI
    Xiangjian Kong, Kai Xu, Robert Bogdan Staszewski, Mingchao Jian, Chunbing Guo
    Guangdong University of Technology · King's College London · University College Dublin
  33. CICC
    2023
    A 52-67GHz Ultra-Compact Bi-directional Gate-switching Cascode Amplifier with Tri-coil Broadband Matching in 40-nm CMOS
    DOI
    Haoyang Jia, Yanjie Wang, Anding Zhu
    University College Dublin · South China University of Technology
  34. JSSC
    2023
    A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness
    DOI
    Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu
    University College Dublin · University of Science and Technology of China
  35. JSSC
    2023
    A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion
    DOI
    Zhong Gao, Martin Fritz, Gerd Spalink, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · University College Dublin
  36. JSSC
    2023
    A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit
    DOI
    Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · NXP · Hong Kong University of Science and Technology · The Hong Kong University of Science and Technology (Guangzhou) · University College Dublin
  37. VLSI
    2023
    A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA
    DOI
    Kai Xu, Bowen Yu, Jun Hu, Yubin Li, Robert Bogdan Staszewski, Hongtao Xu
    Fudan University · University College Dublin
  38. VLSI
    2023
    An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM
    DOI
    Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  39. ISSCC
    2022
    A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs
    DOI
    Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie
    Delft University of Technology · University College Dublin · ソニーSony
  40. ISSCC
    2022
    A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
    DOI
    Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski
    TSMC · University College Dublin
  41. JSSC
    2022
    A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
    DOI
    Simone M. Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael P. Kennedy, Carlo Samori, Salvatore Levantino
    Politecnico di Milano · Qualcomm · Infineon · University College Dublin
  42. JSSC
    2022
    A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection
    DOI
    Amir Bozorg, Robert Bogdan Staszewski
    University College Dublin
  43. JSSC
    2022
    A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking
    DOI
    Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin
  44. JSSC
    2022
    A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters
    DOI
    Amir Bozorg, Robert Bogdan Staszewski
    University College Dublin
  45. JSSC
    2022
    A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range
    DOI
    Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin
  46. JSSC
    2022
    A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC
    DOI
    Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski
    University College Dublin
  47. JSSC
    2022
    A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple
    DOI
    Yue Chen, Jiang Gong, Robert Bogdan Staszewski, Masoud Babaie
    Delft University of Technology · University College Dublin
  48. JSSC
    2022
    A mm-Wave Switched-Capacitor RFDAC
    DOI
    Hieu Minh Nguyen, Jeffrey Sean Walling, Anding Zhu, Robert Bogdan Staszewski
    University College Dublin · Virginia Tech
  49. JSSC
    2022
    Broadband GaN MMIC Doherty Power Amplifier Using Continuous-Mode Combining for 5G Sub-6 GHz Applications
    DOI
    Jingzhou Pang, Chenhao Chu, Jiayan Wu, Zhijiang Dai, Mingyu Li, Songbai He, Anding Zhu
    University College Dublin · Chongqing University · University of Electronic Science and Technology of China
  50. JSSC
    2022
    Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer
    DOI
    Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Mike Keaveney
    University College Dublin · Analog Devices · Limerick Institute of Technology
  51. VLSI
    2022
    A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation
    DOI
    Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie
    Delft University of Technology · University College Dublin