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VLSI · 2022–2026 LIVE

University College Dublin

対象論文Papers 10 · 筆頭著者first author 5 · 著者按分fractional 5.72 · 世界World #20

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Robert Bogdan Staszewski ORCID8
2Teerachot Siriburanon ORCID4
3Sayan Kumar ORCID3
4Feifan Hong ORCID2
4Jiawen Chen ORCID2
4Patchara Sawakewang2
4Pingda Guan ORCID2
4Robert B. Staszewski2
9Chawin Khongprasongsiri ORCID1
9Chunxiao Liu ORCID1
9Viet Nguyen ORCID1
9Yevhenii Mormul ORCID1

対象論文Papers

  1. VLSI
    2026
    A 28-GHz Quadrature LO-Phase-Shifting Digital Wave-Locked Loop (WLL) Achieving 57.2-fs rms Jitter, -80.6-dBc Spur ref , and 0.59-μs Near-Integer Lock Time
    DOI
    Feifan Hong, Jiawen Chen, Chunxiao Liu, Pingda Guan, Robert B. Staszewski, Teerachot Siriburanon
    University College Dublin
  2. VLSI
    2025
    A 0.184mm 2 $W$-Band Single-RTWO-Based Subharmonic RX Achieving 3.72 dB-NF and I/Q Mismatch < 0.8° in 22 nm CMOS
    DOI
    Juncheng Deng, Aodi Li, Junlin Li, Weichen Tao, Shaoqi Yang, Zhongjun Zhang, Yuhao Yang, Xin Cheng, Fujiang Lin, Robert Bogdan Staszewski, Liheng Lou, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  3. VLSI
    2025
    A 24.5-to-45.2-GHz Dual-Injection Clock Multiplier with Folded-Inductor-Based Magnetic-Flux Cancellation Achieving 32.83-fsrms Jitter and 0.037-mm2 Core Area
    DOI
    Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert B. Staszewski, Teerachot Siriburanon
    University College Dublin
  4. VLSI
    2025
    A 31.5-36 GHz Low-Spur Gain-Boosting Charge-Sharing Locking PLL with 54fs Jitter
    DOI
    Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon
    University College Dublin
  5. VLSI
    2025
    A Pipelined-SAR-TDC with Time-Domain Noise-Shaping Self-Calibration
    DOI
    Yevhenii Mormul, Viet Nguyen, Robert Bogdan Staszewski
    University College Dublin
  6. VLSI
    2024
    A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling
    DOI
    Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski
    University College Dublin
  7. VLSI
    2024
    A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement
    DOI
    Xiangjian Kong, Kai Xu, Robert Bogdan Staszewski, Mingchao Jian, Chunbing Guo
    Guangdong University of Technology · King's College London · University College Dublin
  8. VLSI
    2023
    A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA
    DOI
    Kai Xu, Bowen Yu, Jun Hu, Yubin Li, Robert Bogdan Staszewski, Hongtao Xu
    Fudan University · University College Dublin
  9. VLSI
    2023
    An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM
    DOI
    Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu
    University of Science and Technology of China · University College Dublin
  10. VLSI
    2022
    A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation
    DOI
    Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie
    Delft University of Technology · University College Dublin