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VLSI · 2022–2026 LIVE

University of Macau

対象論文Papers 25 · 筆頭著者first author 16 · 著者按分fractional 16.49 · 世界World #4

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Pui-In Mak ORCID12
1Rui P. Martins ORCID12
3Chi-Hang Chan ORCID4
3Mingqiang Guo ORCID4
3Sai-Weng Sin ORCID4
3Yan Zhu4
7Ka-Fai Un ORCID3
7Man-Kay Law ORCID3
7Rui Martins3
7Wei-Han Yu3
7Yang Jiang ORCID3
12Fengen Yuan2
12Haoyu Li2
12Hongjiang Chen ORCID2
12Jingxiang Wang ORCID2
12Jun Yin2
12Kaize Zhang2
12Minglei Zhang ORCID2
12Qiaobo Ma ORCID2
12R. P. Martins2
12Xuchu Mu ORCID2
12Yatao Peng ORCID2
12Yong Chen ORCID2
12Yuefeng Cao ORCID2
25Anyang Zhao ORCID1
25Buhui Rui1
25Chenxi Wang1
25Fei Tan ORCID1
25Guangshu Zhao1
25Hao Su1
25Hao Wu ORCID1
25Haoyang Sang ORCID1
25Jiahao Shi1
25Jiawei Li1
25Jiawei Xu ORCID1
25Jixuan Li1
25Ka-Meng Lei ORCID1
25Kai Xing ORCID1
25Litao Zhang1
25Mo Huang ORCID1
25Ningchao Lin1
25Ran Zhang1
25Shizhan Mo1
25Shousheng Han ORCID1
25Shuliang Pan ORCID1
25Wenhua Gong1
25Xiang-Hui Pan1
25Xianghui Pan ORCID1
25Xinyang Di1
25Xiongjie Zhang ORCID1
25Xiuyuan Zhao1
25Yao Lu1
25Yimeng Wang1
25Yong Huo1
25Yue Wu ORCID1
25Yuhang Peng1
25Yunbo Huang ORCID1
25Zhongyu Zhao1
25Zi-Xuan Xu1

対象論文Papers

  1. VLSI
    2026
    0.144mm 2 Fully-Integrated-Onchip Fast-Converging Background Calibrations for 3-Stage 70.5dB-DR CT Pipelined ADC in 28nm CMOS
    DOI
    Kai Xing, Zi-Xuan Xu, Xiang-Hui Pan, Yan Zhu, Rui P. Martins, Chi-Hang Chan
    University of Macau
  2. VLSI
    2026
    A $3.2 \text{GS} / \mathbf{s}^{2}{ }^{\text {nd }}$-Order Noise-Shaping-Pipelined ADC with 400 MHz-BW 69 dB-SNDR Featuring Gain/Quantizer-Embedded Parallel Voltage/Time-Domain Loop Filter
    DOI
    Yuhang Peng, Shizhan Mo, Liang Qi, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo
    University of Macau · Shanghai Jiao Tong University
  3. VLSI
    2026
    A 0.0257 mm 2 , 1.16 µW, Mask-Efficient KWS SoC with Hybrid Cap-ROM-IMC/SRAM-NMC and Transfer Learning for Flexible Multi-Keyword Recognition
    DOI
    Fei Tan, Zhongyu Zhao, Wei-Han Yu, Ka-Fai Un, Jiawei Xu, Yingzhe Hu, Mahsa Shoaran, Rui P. Martins, Pui-In Mak
    University of Macau · École Polytechnique Fédérale de Lausanne
  4. VLSI
    2026
    A 12-Bit 4-GS/s ADC with PLL-Based Sub-Ranging RO-TDC
    DOI
    Yimeng Wang, Xinyang Di, Jingxiang Wang, Hongjiang Chen, Ran Zhang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo
    University of Macau
  5. VLSI
    2026
    A 14b 500MS/s Pipelined-SAR ADC with Loop-Unrolled Correlated Level Shifting and Rapid Sequential Sampling
    DOI
    Yong Huo, Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui. P. Martins, Chi-Hang Chan
    University of Macau
  6. VLSI
    2026
    A 19.4mW 2.5GS/s Pipelined-SAR ADC Achieving 60.8dB SNDR Employing a Dual-Zero-Compensation Ring Amplifier
    DOI
    Jingxiang Wang, Kaize Zhang, Xiuyuan Zhao, Hongjiang Chen, Haoyu Li, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo
    University of Macau
  7. VLSI
    2026
    A 2D-Extendable $\mathbf{4 8 V}$-1V Ladder-Series-Capacitor Buck Converter for Computing Power Delivery
    DOI
    Zhiguo Tong, Wenjie Yang, Zhewen Yu, Shousheng Han, Rui P. Martins, Yan Lu
    Tsinghua University · University of Macau
  8. VLSI
    2026
    A 54-to-60GHz Cascaded PLL Featuring Implicit Frequency Doubling and Harmonic-Mixing Phase Detector Achieving 53.8fs rms Jitter and −281.1dB FoM N
    DOI
    Yunbo Huang, Zunsong Yang, Li Wang, Kai Cheng, Hongyu Ren, Xiaoyu Shan, Pui-In Mak, Yong Chen, Bo Li
    Chinese Academy of Sciences · University of Macau · Tsinghua University
  9. VLSI
    2026
    A 64-Channel, Low-Power End-to-End Transformer-Based BCI SoC for Efficient Motion Intention Decoding
    DOI
    Fei Tan, Raphael Berner, Zhongyu Zhao, Yuhan Xie, Amirmahdi Joudi, Yiheng Fu, Icare Sakr, Thibault Collin, Vincent Rouanne, Henri Lorach, Ka-Fai Un, Pui-In Mak, Jocelyne Bloch, Gregoire Courtine, Mahsa Shoaran
    École Polytechnique Fédérale de Lausanne · University of Macau
  10. VLSI
    2026
    A Compact Magnetically Coupled Dual-Mode Class-F −1 VCO Covering 5.8−9.97 GHz with 196.2 dBc/Hz FoM and 70-320 kHz 1/f 3 Corner Without Harmonic Tuning
    DOI
    Yue Wu, Yatao Peng, Jiawei Li, Fengen Yuan, Wenhua Gong, Jun Yin, Rui P. Martins, Pui-In Mak
    University of Macau
  11. VLSI
    2026
    A Universal Piezoelectric Energy-Harvesting Interface with Machine Learning-Based Excitation Identification and Cross-Topology MPPT for Diverse Input Vibrations
    DOI
    Guangshu Zhao, Haoyang Sang, Chenxi Wang, Hao Wu, Litao Zhang, Ningchao Lin, Kaixue Ma, Rui P. Martins, Man-Kay Law
    University of Macau · Tianjin University
  12. VLSI
    2025
    A $5.2\mu \mathrm{W}$, 2-to-8-Channel Scalable, Speaker-Tracking Microphone Array Featuring a CNN-Defined AFE
    DOI
    Shuliang Pan, Wei-Han Yu, Fei Tan, Jixuan Li, Ka-Fai Un, Rui P. Martins, Pui-In Mak
    University of Macau · École Polytechnique Fédérale de Lausanne
  13. VLSI
    2025
    A 0.06mm2 14.7-to-20.2GHz Quad-Core VCO Enabled by the Folded Circular Transformer Achieving 201.1dBc/Hz FoMT and 203.4dBc/Hz FoMA
    DOI
    Tincheng Ou, Kunpeng Hu, Hao Xu, Junjie Gu, Yizhuo Wang, Junyan Bi, Wenpeng He, Zhiwei Xu, Man-Kay Law, Na Yan
    Fudan University · Zhejiang University · University of Macau
  14. VLSI
    2025
    A 24-MHz Crystal Oscillator with 6.9-µs Startup Time and 2% Injection- $\Delta$ F Tolerance Using Phase-Interpolator-Assisted Synchronized Injection
    DOI
    Xin Wang, Zixuan Wang, Ka-Meng Lei, Shanhu Wang, Jiafei Yao, Zhikuang Cai, Pui-In Mak, Yufeng Guo
    Nanjing University of Posts and Telecommunications · University of Macau
  15. VLSI
    2025
    A 9.1mW All-5V-CMOS Series-Capacitor AC-DC Converter with CF Reallocation Operations for 85-230VRMS Mains Achieving 85.6% Efficiency at 858mW/cm3 Density
    DOI
    Jiahao Shi, Xuchu Mu, Qiaobo Ma, Yang Jiang, Rui Martins, Pui-In Mak
    University of Macau
  16. VLSI
    2025
    A CRYO-CMOS RF-DAC Based Super-Heterodyne Transmitter for Superconducting Qubit Control
    DOI
    Fengen Yuan, Hao Su, Yating Zou, Yatao Peng, Jun Yin, Fei Yan, Edoardo Charbon, Rui P. Martins, Pui-In Mak
    University of Macau · École Polytechnique Fédérale de Lausanne · Beijing Academy of Quantum Information Sciences
  17. VLSI
    2025
    A PVT-Robust $\text{16GS}/\mathrm{s} 4 \times \text{TI}$ Time-Domain ADC with Vernier-Based Multipath Flash TDC Achieving $25.7 \text{fJ} / \mathrm{c}-\mathrm{s}$ FoM in 28nm CMOS
    DOI
    Haoyu Li, Kaize Zhang, Liang Qi, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo
    University of Macau · Shanghai Jiao Tong University
  18. VLSI
    2025
    A Single-Channel 14B 3GS/s Pipelined ADC in 28nm Technology
    DOI
    Buhui Rui, Xianghui Pan, Yao Lu, Yan Zhu, R. P. Martins, Chi-Hang Chan
    University of Macau
  19. VLSI
    2025
    Matryoshka CSCR: A Reconfigurable Matryoshka-Stacked Continuous-Scalable-Conversion-Ratio Switched-Capacitor DC-DC Converter with 0.1-to-1.7V Input
    DOI
    Yunzhe Yang, Wenyu Peng, Mo Huang, Sijun Du
    Delft University of Technology · University of Macau
  20. VLSI
    2024
    A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur
    DOI
    Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
    Chinese Academy of Sciences · University of Macau · 東京大学The University of Tokyo
  21. VLSI
    2024
    A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density
    DOI
    Xuchu Mu, Yang Jiang, Rui Martins, Pui-In Mak
    University of Macau
  22. VLSI
    2023
    A 0.05-to-3.1A 585mA/mm3 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation
    DOI
    Xiongjie Zhang, Qiaobo Ma, Anyang Zhao, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Martins
    University of Macau · University of Lisbon
  23. VLSI
    2023
    A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces
    DOI
    MoonHyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E.J. Chichilnisky, Boris Murmann, Dante G. Muratore
    Stanford University · University of Macau · Yonsei University · Delft University of Technology
  24. VLSI
    2023
    A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS
    DOI
    Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
    Chinese Academy of Sciences · University of Chinese Academy of Sciences · University of Macau
  25. VLSI
    2023
    A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors
    DOI
    Minglei Zhang, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, R. P. Martins
    University of Macau