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JSSC · 2022–2026 LIVE

University of Padua

対象論文Papers 7 · 筆頭著者first author 3 · 著者按分fractional 2.20 · 世界World #71

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Andrea Bevilacqua ORCID6
2Agata Iesurum ORCID3
3Davide Manente ORCID2
4Andrea Neviani ORCID1
4Lorenzo Tomasin ORCID1
4Lucrezia Navarin ORCID1
4Marta Bagatin ORCID1
4Simone Gerardin ORCID1

対象論文Papers

  1. JSSC
    2026
    A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication
    DOI
    Lucrezia Navarin, Karl Norling, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam, Andrea Neviani, Andrea Bevilacqua
    University of Padua · Infineon
  2. JSSC
    2024
    Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
    DOI
    Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
    University of Padua · Infineon
  3. JSSC
    2023
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  4. JSSC
    2022
    A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
    DOI
    Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
    University of Padua · Lund University · Infineon
  5. JSSC
    2022
    A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
    DOI
    Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
    University of Pavia · University of Padua · Infineon
  6. JSSC
    2022
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
    DOI
    Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · Qualcomm · University of Padua
  7. JSSC
    2022
    Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing
    DOI
    Abhishek Jain, Andrea Mario Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin
    STMicroelectronics · STMicroelectronics · University of Padua