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大学University · イタリアItaly · 2022–2026 LIVE

University of Padua

世界World 25位 (0 pt) · 対象論文Papers 11

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

024682022 ISSCC: 12022 JSSC: 42022 CICC: 12022 ESSERC: 1720222023 JSSC: 1120232024 JSSC: 12024 ESSERC: 12202420252026 JSSC: 112026
ISSCCJSSCCICCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC1––––
JSSC411–1
CICC1––––
ESSERC1–1––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1100.15世界World #112
VLSI Tier 1000.00–
JSSC Tier 1732.20世界World #71
CICC Tier 2100.15世界World #113
A-SSCC Tier 2000.00–
ESSERC Tier 2210.82世界World #74

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. JSSC
    2026
    A 0.13- μ m HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication
    DOI
    Lucrezia Navarin, Karl Norling, Marco Parenzan, Alexander Uran, Stefano Ruzzu, Krithika Rathinam, Andrea Neviani, Andrea Bevilacqua
    University of Padua · Infineon
  2. ESSERC
    2024
    A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs
    DOI
    Luigi Grimaldi, Agata Iesurum, Giovanni Boi, Fabio Versolatto, Giovanni Steffan, Fabio Padovan, Heorhii Koltsov, Andrea Bevilacqua, Dmytro Cherniak
    Infineon · University of Padua
  3. JSSC
    2024
    Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
    DOI
    Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
    University of Padua · Infineon
  4. JSSC
    2023
    A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  5. CICC
    2022
    A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
    DOI
    Francesco Buccoleri, Simone M. Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  6. ESSERC
    2022
    A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS
    DOI
    Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua
    University of Padua · Infineon
  7. ISSCC
    2022
    A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
    DOI
    Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · University of Padua
  8. JSSC
    2022
    A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
    DOI
    Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua
    University of Padua · Lund University · Infineon
  9. JSSC
    2022
    A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
    DOI
    Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
    University of Pavia · University of Padua · Infineon
  10. JSSC
    2022
    A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
    DOI
    Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
    Politecnico di Milano · Infineon · Qualcomm · University of Padua
  11. JSSC
    2022
    Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing
    DOI
    Abhishek Jain, Andrea Mario Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin
    STMicroelectronics · STMicroelectronics · University of Padua