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ESSERC · 2022–2026 LIVE

University of Pavia

対象論文Papers 13 · 筆頭著者first author 10 · 著者按分fractional 9.64 · 世界World #10

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank著者Author論文数Papers
1Andrea Mazzanti ORCID5
2Rinaldo Castello ORCID4
3Danilo Manstretta ORCID3
3Edoardo Bonizzoni ORCID3
3Guglielmo De Filippi ORCID3
3Lorenzo Piotto ORCID3
3Piero Malcovati ORCID3
8A. Cabrini2
8Andrea Bilato ORCID2
8Simone Lecchi2
11Andrea Vigna1
11Antonio Aprile ORCID1
11L. Iannelli1
11Lara Novaresi1
11Luca Canato1
11Mahmoud M. Pirbazari ORCID1
11Nicola Cordioli1
11R. Vignali1

対象論文Papers

  1. ESSERC
    2025
    28 M Weights $\times$ TOPs $/ \mathrm{W}/\text{mm}^{2}$ PCM-Based Analog in-Memory Computing Core with 8 $512 \times 512{}$-Weight Layers in 28 nm FD-SOI CMOS
    DOI
    M. Pasotti, R. Zurla, J. J. Bertolini Agnoletto, E. Calvetti, A. Antolini, L. Croce, G. Desoli, L. Iannelli, A. Lico, R. Vignali, F. Zavalloni, E. Franchi Scarselli, A. Cabrini
    STMicroelectronics · University of Bologna · University of Pavia
  2. ESSERC
    2025
    A 600-V Fully-Integrated Hybrid-Burst Capacitor Coupling Level Shifter with 130-V/ns Common Mode Transient Immunity
    DOI
    Luca Canato, Andrea Vigna, Edoardo Bonizzoni, Piero Malcovati
    University of Pavia
  3. ESSERC
    2024
    A D-Band LNA Exploiting Ultra-Wideband Sixth-Order Matching Networks in SiGe BiCMOS
    DOI
    Guglielmo De Filippi, Lorenzo Piotto, Andrea Mazzanti
    University of Pavia
  4. ESSERC
    2024
    D-band Stacked Common-Base Power Amplifier with 19.2dBm oP1dB in 55 nm SiGe BiCMOS
    DOI
    Andrea Bilato, Mahmoud M. Pirbazari, Andrea Mazzanti
    University of Pavia
  5. ESSERC
    2023
    A 20mW 130-175GHz Phase Shifter with Meandered λ/2 TLINEs in BiCMOS 55nm
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Andrea Bilato, Andrea Mazzanti
    University of Pavia
  6. ESSERC
    2023
    An Interferer-Tolerant RX with Translational Positive Feedback for 5G NR Applications Achieving 3.4 dB NF and 18 dBm OOB IIP3
    DOI
    Simone Lecchi, Danilo Manstretta, Rinaldo Castello
    University of Pavia
  7. ESSERC
    2022
    A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology
    DOI
    Nicola Cordioli, Danilo Manstretta, Rinaldo Castello
    University of Pavia
  8. ESSERC
    2022
    A Compact 2.5-nJ Energy/Conversion NPN-Based Temperature-to-Digital Converter with a Fully Current-Mode Processing Architecture
    DOI
    Antonio Aprile, Michele Folz, Daniele Gardino, Piero Malcovati, Edoardo Bonizzoni
    University of Pavia
  9. ESSERC
    2022
    A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti
    University of Pavia · Infineon
  10. ESSERC
    2022
    A PMUT Transceiver Front-End with 100-V TX Driver and Low-Noise Voltage Amplifier in BCD-SOI Technology
    DOI
    Lara Novaresi, Piero Malcovati, Andrea Mazzanti, Edoardo Bonizzoni, Marco Terenzi, Stefano Ottaviani, Davide Ugo Ghisu, Fabio Quaglia, Alessandro Stuart Savoia
    University of Pavia · STMicroelectronics · Roma Tre University
  11. ESSERC
    2022
    An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power Applications
    DOI
    M. Carissimi, C. Auricchio, E. Calvetti, L. Capecchi, M. Torres, S. Zanchi, P. Gupta, R. Zurla, A. Cabrini, D. Gallinari, F. Disegni, M. Borghi, E. Palumbo, A. Redaelli, M. Pasotti
    STMicroelectronics · STMicroelectronics · University of Pavia
  12. ESSERC
    2022
    An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier
    DOI
    Jin Jin, Simone Lecchi, Rinaldo Castello, Danilo Manstretta
    Southeast University · University of Pavia
  13. ESSERC
    2022
    Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz
    DOI
    Rinaldo Castello
    University of Pavia