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大学University · イタリアItaly · 2022–2026 LIVE

University of Pavia

世界World 24位 (0.5 pt) · 対象論文Papers 40

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

051015202022 ISSCC: 12022 VLSI: 12022 JSSC: 62022 CICC: 12022 ESSERC: 71620222023 CICC: 32023 ESSERC: 2520232024 JSSC: 22024 CICC: 12024 ESSERC: 2520242025 ISSCC: 12025 JSSC: 32025 CICC: 12025 ESSERC: 2720252026 ISSCC: 12026 JSSC: 52026 CICC: 172026
ISSCCVLSIJSSCCICCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC1––11
VLSI1––––
JSSC6–235
CICC13111
ESSERC7222–

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1332.40世界World #77
VLSI Tier 1110.38世界World #78
JSSC Tier 11687.06世界World #42
CICC Tier 2754.61世界World #30
A-SSCC Tier 2000.00–
ESSERC Tier 213109.64世界World #10

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    An Ultra-Low-Power Capacitive Stacking Receiver Front-End with a PVT-Robust Switched-Capacitor-Based Feed-Forward IM3 Cancellation Technique
    DOI
    Jin Jin, Zhepu Xu, Bowei Xiao, Guisheng Yan, Danilo Manstretta, Wen Wu, Tongde Huang
    Nanjing University of Science and Technology · University of Pavia
  2. ISSCC
    2026
    A 48-to-82.5GHz CMOS Split-Tail Gilbert-Cell Frequency Doubler Achieving 11% PAE at 8.5dBm Output Power
    DOI
    Jismal Jamal, Lorenzo Piotto, Federico Vecchi, Mahmoud M. Pirbazari, Andrea Mazzanti
    University of Pavia · STMicroelectronics
  3. JSSC
    2026
    A +43.3-dBm IIP 3 , Low-Power Transimpedance Amplifier Employing a Switched-Capacitor Amplifier-Based Transition-Band Pole-Zero Doublets Compensation Technique
    DOI
    Bowei Xiao, Jin Jin, Haipeng Bai, Wen Wu, Danilo Manstretta, Tongde Huang
    Nanjing University of Science and Technology · University of Pavia
  4. JSSC
    2026
    A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm 2
    DOI
    Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini
    STMicroelectronics · University of Bologna · University of Pavia
  5. JSSC
    2026
    A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS
    DOI
    Daniele Lodi Rizzini, Francesco Tesolin, Michele Rossoni, Riccardo Moleri, Filippo Osio, Andrea Mazzanti, Andrea L. Lacaita, Simone M. Dartizio, Salvatore Levantino
    Politecnico di Milano · University of Pavia
  6. JSSC
    2026
    Design Insights Into Sixth-Order Matching Networks for a 105–175-GHz Ultra-Wideband SiGe BiCMOS LNA
    DOI
    Guglielmo De Filippi, Lorenzo Piotto, Andrea Bilato, Andrea Mazzanti
    University of Pavia
  7. JSSC
    2026
    High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI
    DOI
    Alessio Antolini, Andrea Lico, Francesco Zavalloni, Lorenzo Greco, Riccardo Zurla, Jacopo Bertolini, Riccardo Vignali, Luca Iannelli, Emanuela Calvetti, Marco Pasotti, Alessandro Cabrini, Eleonora Franchi Scarselli
    University of Bologna · STMicroelectronics · University of Pavia
  8. CICC
    2025
    A 106.1dB DR, 450μA Idle Current Class-H Piezoelectric MEMS MicroSpeaker Driver with Envelope Tracking, Digital and Analog Inputs and Less Than 2.1μs Latency
    DOI
    F. Rezzi, V. Colonna, G. Gandolfi, S. Fusetto, M. Chiabrera, A. Savo, M. Costagliola, R. Stella, M. Bulzi, S. Radosav, D. Granozio, G. Alfieri, A. Gemelli, P. Malcovati, E. Bonizzoni
    University of Pavia
  9. ESSERC
    2025
    28 M Weights $\times$ TOPs $/ \mathrm{W}/\text{mm}^{2}$ PCM-Based Analog in-Memory Computing Core with 8 $512 \times 512{}$-Weight Layers in 28 nm FD-SOI CMOS
    DOI
    M. Pasotti, R. Zurla, J. J. Bertolini Agnoletto, E. Calvetti, A. Antolini, L. Croce, G. Desoli, L. Iannelli, A. Lico, R. Vignali, F. Zavalloni, E. Franchi Scarselli, A. Cabrini
    STMicroelectronics · University of Bologna · University of Pavia
  10. ESSERC
    2025
    A 600-V Fully-Integrated Hybrid-Burst Capacitor Coupling Level Shifter with 130-V/ns Common Mode Transient Immunity
    DOI
    Luca Canato, Andrea Vigna, Edoardo Bonizzoni, Piero Malcovati
    University of Pavia
  11. ISSCC
    2025
    33.3 A 125-to-170GHz Power-Efficient Phase Shifter in SiGe BiCMOS with Outphasing Gain and Phase Corrections
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Andrea Mazzanti
    University of Pavia
  12. JSSC
    2025
    A 78.2-dB Dynamic Range Shunt-Based Current Sensor for BLDC Motor Control With 2.75- μ s Conversion Time and 0.4-mm² Active Area
    DOI
    Antonio Aprile, Jaya Satyanarayana Yarragunta, Andreas Fugger, Francesco Conzatti, Edoardo Bonizzoni, Piero Malcovati
    University of Pavia · Infineon
  13. JSSC
    2025
    AM–AM and AM–PM Distortion in D -Band BiCMOS Vector-Interpolation Phase Shifters
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Andrea Bilato, Andrea Mazzanti
    University of Pavia
  14. JSSC
    2025
    Analysis and Design of a CMOS E-Band Frequency Quadrupler With Transformer-Based Harmonic Reflectors
    DOI
    Paolo Ricco, Gianfranco Avitabile, Danilo Manstretta
    Polytechnic University of Bari · University of Pavia
  15. CICC
    2024
    Interferer-Tolerant RX Front-End Architectures
    DOI
    Danilo Manstretta
    University of Pavia
  16. ESSERC
    2024
    A D-Band LNA Exploiting Ultra-Wideband Sixth-Order Matching Networks in SiGe BiCMOS
    DOI
    Guglielmo De Filippi, Lorenzo Piotto, Andrea Mazzanti
    University of Pavia
  17. ESSERC
    2024
    D-band Stacked Common-Base Power Amplifier with 19.2dBm oP1dB in 55 nm SiGe BiCMOS
    DOI
    Andrea Bilato, Mahmoud M. Pirbazari, Andrea Mazzanti
    University of Pavia
  18. JSSC
    2024
    A 14–32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Gianluca Brozzetti, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti
    University of Pavia · Infineon
  19. JSSC
    2024
    An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS
    DOI
    Antonio Aprile, Michele Folz, Daniele Gardino, Piero Malcovati, Edoardo Bonizzoni
    University of Pavia
  20. CICC
    2023
    A 0.06-mm2 Current-Mode Noise-Shaping SAR based Temperature-to-Digital Converter with a 4.9-nJ Energy/Conversion
    DOI
    Antonio Aprile, Michele Folz, Daniele Gardino, Piero Malcovati, Edoardo Bonizzoni
    University of Pavia
  21. CICC
    2023
    An 87.2%-peak efficiency 4.1 W-output power switchedcapacitor 3-level inverting buck-boost dc-dc converter
    DOI
    S. Fusetto, E. Moisello, H. Petersen, S. Abedinpour, P. Malcovati, E. Bonizzoni
    University of Pavia · Renesas Electronics (United States)
  22. CICC
    2023
    Analog Front-End Circuits for MEMS Microphones
    DOI
    Piero Malcovati
    University of Pavia
  23. ESSERC
    2023
    A 20mW 130-175GHz Phase Shifter with Meandered λ/2 TLINEs in BiCMOS 55nm
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Andrea Bilato, Andrea Mazzanti
    University of Pavia
  24. ESSERC
    2023
    An Interferer-Tolerant RX with Translational Positive Feedback for 5G NR Applications Achieving 3.4 dB NF and 18 dBm OOB IIP3
    DOI
    Simone Lecchi, Danilo Manstretta, Rinaldo Castello
    University of Pavia
  25. CICC
    2022
    Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of Bandwidth
    DOI
    Nimesh Nadishka Miral, Karan Sohal, Danilo Manstretta, Rinaldo Castello
    University of Pavia
  26. ESSERC
    2022
    A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology
    DOI
    Nicola Cordioli, Danilo Manstretta, Rinaldo Castello
    University of Pavia
  27. ESSERC
    2022
    A Compact 2.5-nJ Energy/Conversion NPN-Based Temperature-to-Digital Converter with a Fully Current-Mode Processing Architecture
    DOI
    Antonio Aprile, Michele Folz, Daniele Gardino, Piero Malcovati, Edoardo Bonizzoni
    University of Pavia
  28. ESSERC
    2022
    A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology
    DOI
    Lorenzo Piotto, Guglielmo De Filippi, Daniele Dal Maistro, Simone Erba, Andrea Mazzanti
    University of Pavia · Infineon
  29. ESSERC
    2022
    A PMUT Transceiver Front-End with 100-V TX Driver and Low-Noise Voltage Amplifier in BCD-SOI Technology
    DOI
    Lara Novaresi, Piero Malcovati, Andrea Mazzanti, Edoardo Bonizzoni, Marco Terenzi, Stefano Ottaviani, Davide Ugo Ghisu, Fabio Quaglia, Alessandro Stuart Savoia
    University of Pavia · STMicroelectronics · Roma Tre University
  30. ESSERC
    2022
    An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power Applications
    DOI
    M. Carissimi, C. Auricchio, E. Calvetti, L. Capecchi, M. Torres, S. Zanchi, P. Gupta, R. Zurla, A. Cabrini, D. Gallinari, F. Disegni, M. Borghi, E. Palumbo, A. Redaelli, M. Pasotti
    STMicroelectronics · STMicroelectronics · University of Pavia
  31. ESSERC
    2022
    An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier
    DOI
    Jin Jin, Simone Lecchi, Rinaldo Castello, Danilo Manstretta
    Southeast University · University of Pavia
  32. ESSERC
    2022
    Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz
    DOI
    Rinaldo Castello
    University of Pavia
  33. ISSCC
    2022
    Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM
    DOI
    Alessandro Franceschin, Domenico Riccardi, Andrea Mazzanti
    University of Pavia
  34. JSSC
    2022
    A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter
    DOI
    Jin Jin, Jianhui Wu, Rinaldo Castello, Danilo Manstretta
    Southeast University · University of Pavia
  35. JSSC
    2022
    A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
    DOI
    Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua
    University of Pavia · University of Padua · Infineon
  36. JSSC
    2022
    A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS
    DOI
    Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui P. Martins
    University of Macau · University of Pavia
  37. JSSC
    2022
    Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology
    DOI
    Farhad Bozorgi, Melchiorre Bruccoleri, Elham Rahimi, Matteo Repossi, Francesco Svelto, Andrea Mazzanti
    University of Pavia · Barkhausen Institut · STMicroelectronics · Silicon Austria Labs (Austria)
  38. JSSC
    2022
    E-Band Frequency Sextupler With >35 dB Harmonics Rejection Over 20 GHz Bandwidth in 55 nm BiCMOS
    DOI
    Mahmoud M. Pirbazari, Andrea Mazzanti
    University of Pavia
  39. JSSC
    2022
    Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance
    DOI
    Alessandro Franceschin, Domenico Riccardi, Andrea Mazzanti
    University of Pavia · STMicroelectronics · Infineon
  40. VLSI
    2022
    A Magnetically Coupled Dual-Core 154-GHz Class-F Oscillator with -177.1 FoM and -87 dBc/Hz PN at 1-MHz Offset in a 22-nm FDSOI with Third-Harmonic Extraction
    DOI
    Sarthak Sharma, Hao Gao, Gernot Hueber, Andrea Mazzanti
    University of Pavia · Silicon Austria Labs (Austria) · Eindhoven University of Technology