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大学University · 日本Japan · 2022–2026 LIVE

東京大学The University of Tokyo

The University of Tokyo

日本Japan 2位 (83 pt) · 世界World 25位 (0 pt) · 対象論文Papers 33

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

02468102022 VLSI: 12022 JSSC: 32022 A-SSCC: 32022 ESSERC: 1820222023 VLSI: 32023 JSSC: 12023 CICC: 1520232024 ISSCC: 12024 VLSI: 12024 JSSC: 12024 ESSERC: 2520242025 ISSCC: 22025 VLSI: 22025 JSSC: 22025 A-SSCC: 3920252026 ISSCC: 12026 VLSI: 22026 JSSC: 22026 CICC: 162026
ISSCCVLSIJSSCCICCA-SSCCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
ISSCC––121
VLSI13122
JSSC31122
CICC–1––1
A-SSCC3––3–
ESSERC1–2––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1433.36日本Japan #2 · 世界World #69
VLSI Tier 1977.28日本Japan #2 · 世界World #24
JSSC Tier 1987.87日本Japan #2 · 世界World #65
CICC Tier 2221.89日本Japan #3 · 世界World #85
A-SSCC Tier 2654.43日本Japan #1 · 世界World #22
ESSERC Tier 2311.58日本Japan #2 · 世界World #53

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. CICC
    2026
    A 10-bit 20-GS/s 4-Channel Time-Interleaved DAC Employing Hybrid-Segmentation in 28-nm CMOS
    DOI
    Yunjie Chen, Duran Ckristian, Koji Asami, Sota Kano, Ritaro Takenaka, Zolboo Byambadorj, Masahiro Ishida, Akio Higo, Tetsuya Iizuka
    東京大学The University of Tokyo · アドバンテストAdvantest
  2. ISSCC
    2026
    A 157fs rms -Jitter, −73dBc-Fractional-Spur, Calibration-Free Cascaded SPLL Employing Robust Feedforward Noise Cancellation and MMD-Based Quantization-Error Cancellation with a 60MHz Reference
    DOI
    Haoming Zhang, Yongjun He, Yuyang Zhu, Huanyu Ren, Tetsuya Iizuka
    東京大学The University of Tokyo
  3. JSSC
    2026
    An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators
    DOI
    Ritaro Takenaka, Tetsuya Iizuka
    東京大学The University of Tokyo
  4. JSSC
    2026
    Fractional-N Frequency Synthesis Based on Ring- LC Cascaded PLL With Calibration-Free Noise Cancellation Techniques
    DOI
    Haoming Zhang, Yongjun He, Yuyang Zhu, Huanyu Ren, Tetsuya Iizuka
    東京大学The University of Tokyo
  5. VLSI
    2026
    4.5-W 5-V-Input DC-DC Converter with Six Isolated 15-V Outputs Achieving 175-kV/μs CMTI Without Signal Isolators
    DOI
    Yichen Zhang, Yaogan Liang, Michihiro Ide, Makoto Takamiya
    東京大学The University of Tokyo
  6. VLSI
    2026
    A 91.9dB-SNDR 100kHz-BW DT $\boldsymbol{\Delta} \boldsymbol{\Sigma}$ ADC Employing Thermal Noise Suppression Techniques with Gain-Switched Dynamic Self-Quenching FIA
    DOI
    Ximing Wang, Jiaao Yu, Yunjie Chen, Haoming Zhang, Yuyang Zhu, Tetsuya Iizuka
    東京大学The University of Tokyo
  7. A-SSCC
    2025
    A 2.6GHz Inductorless PLL with Configurable-Duty-Cycle Ring Oscillator and Zero-ISF Subsampling Phase Detector Achiving -70dBc Reference Spur and 186fs RMS Jitter
    DOI
    Yuyang Zhu, Haoming Zhang, Zunsong Yang, Yongjun He, Huanyu Ren, Fumiya Sakuma, Ritaro Takenaka, Sota Kano, Ximing Wang Wang, Tetsuya Lizuka
    東京大学The University of Tokyo · Chinese Academy of Sciences
  8. A-SSCC
    2025
    FPGA Accelerator for 398bit, (2,2)-Isogeny Based PostQuantum Cryptography
    DOI
    Kosei Nakamura, Makoto Ikeda
    東京大学The University of Tokyo
  9. A-SSCC
    2025
    Low-latency FPGA Design of Attribute-based Encryption Accelerator over BLS12-381 Curve
    DOI
    Anawin Opasatian, Momoko Fukuda, Makoto Ikeda
    東京大学The University of Tokyo
  10. ISSCC
    2025
    13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40 th Mask Cost
    DOI
    Jaewon Shin, Rei Sumikawa, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge
    東京大学The University of Tokyo
  11. ISSCC
    2025
    A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation
    DOI
    Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
    東京大学The University of Tokyo
  12. JSSC
    2025
    A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation
    DOI
    Haoming Zhang, Yuyang Zhu, Masaru Osada, Tetsuya Iizuka
    東京大学The University of Tokyo
  13. JSSC
    2025
    A Harmonic-Mixer-Based Fractional- N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation
    DOI
    Haoming Zhang, Masaru Osada, Yuyang Zhu, Tetsuya Iizuka
    東京大学The University of Tokyo
  14. VLSI
    2025
    A 76.5-dB Dynamic-Range 8-bit 100-MS/s Variable-Range SAR ADC
    DOI
    Ritaro Takenaka, Sota Kano, Tetsuya Iizuka
    東京大学The University of Tokyo
  15. VLSI
    2025
    An 11.9-ENOB 560-MS/s Subranging ADC Employing Amplifier-Switching Architecture with Multi-Threshold Comparators
    DOI
    Ritaro Takenaka, Tetsuya Iizuka
    東京大学The University of Tokyo
  16. ESSERC
    2024
    A 28-nm 0.8M-weights/mm2 9.1-TOPS/mm2 SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC
    DOI
    Kota Shiba, Zhijie Zhan, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    TSMC（日本拠点）TSMC Japan · 東京大学The University of Tokyo · TSMC
  17. ESSERC
    2024
    A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, –91.9-dBc Reference Spur and –259-dB Jitter-Power FOM
    DOI
    Hongyu Ren, Yunbo Huang, Zunsong Yang, Tianle Chen, Xianghe Meng, Weiwei Yan, Weidong Zhang, Zhongmao Li, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
    Chinese Academy of Sciences · University of Macau · 東京大学The University of Tokyo · Tsinghua University
  18. ISSCC
    2024
    17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes
    DOI
    Naoki Miura, Hiroaki Taguchi, Kazuyoshi Watanabe, Masaya Nohara, Tatsuyuki Makita, Masahiro Tanabe, Takahiro Wakimoto, Shohei Kumagai, Hideyuki Nosaka, Atsushi Aratake, Toshihiro Okamoto, Shun Watanabe, Jun Takeya, Takeshi Komatsu
    NTT · 東京大学The University of Tokyo · パイクリスタルPI-CRYSTAL
  19. JSSC
    2024
    A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering
    DOI
    Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
    東京大学The University of Tokyo
  20. VLSI
    2024
    A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur
    DOI
    Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li
    Chinese Academy of Sciences · University of Macau · 東京大学The University of Tokyo
  21. CICC
    2023
    Digital Gate ICs for Driving and Sensing Power Devices to Achieve Low-Loss, Low-Noise, and Highly Reliable Power Electronic Systems
    DOI
    Dibo Zhang, Kohei Horii, Katsuhiro Hata, Makoto Takamiya
    東京大学The University of Tokyo
  22. JSSC
    2023
    A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
    DOI
    Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    東京大学The University of Tokyo
  23. VLSI
    2023
    A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
    DOI
    Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda
    東京大学The University of Tokyo
  24. VLSI
    2023
    A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load
    DOI
    Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
    東京大学The University of Tokyo
  25. VLSI
    2023
    Circuit designs for practical-scale fault-tolerant quantum computing
    DOI
    Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto
    NTT · 慶應義塾大学Keio University · 東京大学The University of Tokyo · 名古屋大学Nagoya University · 科学技術振興機構JST
  26. A-SSCC
    2022
    A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
    DOI
    Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    東京大学The University of Tokyo
  27. A-SSCC
    2022
    F-LIC: FPGA-based Learned Image Compression with a Fine-grained Pipeline
    DOI
    Heming Sun, Qingyang Yi, Fangzheng Lin, Lu Yu, Jiro Katto, Masahiro Fujita
    早稲田大学Waseda University · Zhejiang University · 東京大学The University of Tokyo
  28. A-SSCC
    2022
    High-speed and energy-efficient crypto-processor for post-quantum cryptography CRYSTALS-Kyber
    DOI
    Taishin Shimada, Makoto Ikeda
    東京大学The University of Tokyo
  29. ESSERC
    2022
    An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering
    DOI
    Masaru Osada, Zule Xu, Tetsuya Iizuka
    東京大学The University of Tokyo
  30. JSSC
    2022
    A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
    DOI
    Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
    東京大学The University of Tokyo
  31. JSSC
    2022
    A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC
    DOI
    Hao Qiu, Takayasu Sakurai, Makoto Takamiya
    Nanjing University · 東京大学The University of Tokyo
  32. JSSC
    2022
    A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration
    DOI
    Zule Xu
    東京大学The University of Tokyo
  33. VLSI
    2022
    A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter and −240-dB FOMjitter
    DOI
    Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
    東京大学The University of Tokyo