VLSI · 2022–2026 LIVE

東京大学The University of Tokyo

対象論文Papers 9 · 筆頭著者first author 7 · 著者按分fractional 7.28 · 日本Japan #2 · 世界World #24

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Tetsuya Iizuka ORCID	6
2	Masaru Osada ORCID	2
2	Ritaro Takenaka	2
2	Yuyang Zhu ORCID	2
2	Zunsong Yang ORCID	2
6	Atsutake Kosuge ORCID	1
6	Haoming Zhang ORCID	1
6	Jiaao Yu	1
6	Kota Shiba ORCID	1
6	Makoto Takamiya ORCID	1
6	Michihiro Ide ORCID	1
6	Mototsugu Hamada ORCID	1
6	Rei Sumikawa	1
6	Shuowei Li	1
6	Sota Kano	1
6	Tadahiro Kuroda ORCID	1
6	Wang Liao ORCID	1
6	Ximing Wang	1
6	Yao-Chung Hsu	1
6	Yaogan Liang	1
6	Yichen Zhang	1
6	Yunjie Chen	1
6	Zule Xu ORCID	1

対象論文Papers

VLSI
2026

4.5-W 5-V-Input DC-DC Converter with Six Isolated 15-V Outputs Achieving 175-kV/μs CMTI Without Signal Isolators
DOI
Yichen Zhang, Yaogan Liang, Michihiro Ide, Makoto Takamiya

東京大学The University of Tokyo
VLSI
2026

A 91.9dB-SNDR 100kHz-BW DT $\boldsymbol{\Delta} \boldsymbol{\Sigma}$ ADC Employing Thermal Noise Suppression Techniques with Gain-Switched Dynamic Self-Quenching FIA
DOI
Ximing Wang, Jiaao Yu, Yunjie Chen, Haoming Zhang, Yuyang Zhu, Tetsuya Iizuka

東京大学The University of Tokyo
VLSI
2025

A 76.5-dB Dynamic-Range 8-bit 100-MS/s Variable-Range SAR ADC
DOI
Ritaro Takenaka, Sota Kano, Tetsuya Iizuka

東京大学The University of Tokyo
VLSI
2025

An 11.9-ENOB 560-MS/s Subranging ADC Employing Amplifier-Switching Architecture with Multi-Threshold Comparators
DOI
Ritaro Takenaka, Tetsuya Iizuka

東京大学The University of Tokyo
VLSI
2024

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur
DOI
Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li

Chinese Academy of Sciences · University of Macau · 東京大学The University of Tokyo
VLSI
2023

A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
DOI
Atsutake Kosuge, Rei Sumikawa, Yao-Chung Hsu, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda

東京大学The University of Tokyo
VLSI
2023

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load
DOI
Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka

東京大学The University of Tokyo
VLSI
2023

Circuit designs for practical-scale fault-tolerant quantum computing
DOI
Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto

NTT · 慶應義塾大学Keio University · 東京大学The University of Tokyo · 名古屋大学Nagoya University · 科学技術振興機構JST
VLSI
2022

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter and −240-dB FOMjitter
DOI
Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka

東京大学The University of Tokyo