VLSI · 2022–2026 LIVE

Yonsei University

対象論文Papers 22 · 筆頭著者first author 17 · 著者按分fractional 13.33 · 韓国Korea #2 · 世界World #6

所属著者Affiliated authors

ORCID が一致する著者は同一人物としてまとめています。それ以外は表記ごとに別人として扱います。Authors sharing an ORCID are merged; other spellings are listed separately.

順位Rank	著者Author	論文数Papers
1	Youngcheol Chae ORCID	13
2	Seong-Ook Jung ORCID	4
2	Taejune Jeon ORCID	4
4	Junghyun Yoon ORCID	3
5	Byungchoul Park ORCID	2
5	Dongseok Cho ORCID	2
5	Hee Young Kim	2
5	Heon-Jin Choi ORCID	2
5	Hyun-Seung Choi ORCID	2
5	Jeonghyeok You	2
5	Ji-Young Kim ORCID	2
5	Ju Young Lee	2
5	Keonhee Cho ORCID	2
5	Ki Jun Yu	2
5	Kyungmin Kang ORCID	2
5	Myung-Jae Lee ORCID	2
5	Sanghoon Lee	2
5	Seokho Yoon	2
5	Taeryeong Kim	2
20	Changuk Lee ORCID	1
20	Chanmin Park ORCID	1
20	Chanwoo Lee	1
20	Daerl Park	1
20	Danbi Ahn	1
20	Donggun Lee	1
20	Dongseok Seo	1
20	Doyoon Eom	1
20	Eunee Lee	1
20	Eunkyu Hwang	1
20	Eunsung Park	1
20	Giseok Kim ORCID	1
20	Hohyun Chae	1
20	Hoichang Jeong ORCID	1
20	Hyeonho Han ORCID	1
20	Hyunchul Yoon ORCID	1
20	Jaehyun Kim	1
20	Jang-Ung Park	1
20	Jisang Oh ORCID	1
20	Joo-Hyun Kim	1
20	Kiryong Kim ORCID	1
20	Kwanseo Park ORCID	1
20	Kyeongrim Baek	1
20	Kyoungseok Song	1
20	Kyuho Jason Lee ORCID	1
20	Minkyoung Yang	1
20	Sang Hoon Park	1
20	Sangho Rhee	1
20	Sekeon Kim ORCID	1
20	Seonghun Yang	1
20	Shinil Cho	1
20	Suhyeon Nam	1
20	Sun-woong Byun	1
20	Tae Wook Kim ORCID	1
20	Teawoong Kim	1
20	Won Gi Chung	1
20	Woo-Young Choi ORCID	1
20	Woojun Choi ORCID	1
20	Yerin Youn	1
20	Yigi Kwon ORCID	1
20	Yong Lim ORCID	1
20	Yoondeok Na ORCID	1

対象論文Papers

VLSI
2026

A 16-Channel Neural Recording IC with Spike-Driven Adaptive-Basis Compressive Sensing
DOI
Sanghoon Lee, Soohyun Yun, Seokho Yoon, Kyungmin Kang, Taejune Jeon, Sang Hoon Park, Ju Young Lee, Won Gi Chung, Jang-Ung Park, Ki Jun Yu, Joonsung Bae, Youngcheol Chae

Yonsei University · Kangwon National University
VLSI
2026

A 16.8-33.6 Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance Under Deep SSC
DOI
Jongwha Kim, Yongwoo Jo, Seongyun Min, Juntak Chun, Yuhwan Shin, Hyunjun Song, Seohyeon Kwak, Kwanseo Park, Jaehyouk Choi

Seoul National University · Samsung · Yonsei University
VLSI
2026

A 1MHz-BW 90.1dB-SNDR CT Zoom ADC with Mismatch Error Shaping Preserving Full-Scale Input Range
DOI
Junghyun Yoon, Zhaonan Lu, Yong Lim, Zhichao Tan, Youngcheol Chae

Yonsei University · Zhejiang University
VLSI
2026

A 256-Channel, 32-Interconnect, 1.25-NEF, in Vitro and In Vivo Neural Interface With Auto-Calibrated Input Impedance Boosting and on-Chip Spike Detection for Flexible Capacitive Microelectrode Array
DOI
Yiyang Chen, Suhyeon Nam, Sun-woong Byun, Pietro Velcich, Shinil Cho, Chanwoo Lee, Ju Young Lee, Sean Weaver, Enrico Brugnolotto, Eunkyu Hwang, Dongseok Seo, Eunee Lee, Ki Jun Yu, Woojun Choi, Taekwang Jang

ETH Zurich · Yonsei University · Institut Català de Nanociència i Nanotecnologia
VLSI
2026

A 3.25-Gb/S 0.74-pJ/bit IR-UWB Transmitter Using Edge-Reference Differential Phase Shift Keying (ER-DPSK)
DOI
Donggun Lee, Kyoungseok Song, Sangho Rhee, Tae Wook Kim

Yonsei University
VLSI
2026

A SPAD-Based iToF Flash LiDAR Sensor with a Coarse-Fine Operation Scheme Robust Against Strong Background Light
DOI
Dongseok Cho, Hyun-Seung Choi, Injun Park, Yoondeok Na, Seonghun Yang, Minkyoung Yang, Yerin Youn, Jimin Cheon, Myung-Jae Lee, Youngcheol Chae

Yonsei University
VLSI
2026

Back-Illuminated CMOS-SPAD with Full-Surround Anode Structure Achieving Sub-50 ps Timing Jitter for High-Precision Physical-AI Sensors
DOI
Joo-Hyun Kim, Doyoon Eom, Hyun-Seung Choi, Eunsung Park, Woo-Young Choi, Myung-Jae Lee

Yonsei University
VLSI
2026

HCNP: A 70.2 TOPS/W Hybrid CIM-NPU Processor with In-Streaming Processing for Energy-Efficient CNN/Transformer Acceleration in HMD
DOI
Seungbin Kim, Hoichang Jeong, Dongwook Kim, Jiwon Kim, Kyuho Jason Lee

Ulsan National Institute of Science and Technology · Yonsei University
VLSI
2025

A 10kHz-BW, 86.7dB-SNDR, 176.8dB-FoM, LNA-Embedded CT $\mathbf{\Delta}\mathbf{\Sigma}$ ADC for Closed-Loop Neural Recording
DOI
Sanghoon Lee, Junghyun Yoon, Taejune Jeon, Danbi Ahn, Soohyun Yun, Hee Young Kim, Joonsung Bae, Youngcheol Chae

Yonsei University · Kangwon National University
VLSI
2025

A 91.2dB-SNDR 250kHz-BW CT Zoom ADC Achieving a 6-Bit Linear Zoom-in with Interstage LPF and 1.5-Bit DAC
DOI
Junghyun Yoon, Youngcheol Chae

Yonsei University
VLSI
2025

A Fully Balanced Biphasic Neurostimulator with Body-Coupled Powering and Full-Duplex Communication Via Baseband Load Shift Keying
DOI
Taejune Jeon, Kyungmin Kang, Soohyun Yun, Seokho Yoon, Byeongseol Kim, Joonsung Bae, Youngcheol Chae

Yonsei University · Kangwon National University
VLSI
2024

A 30fps $\mathbf{64}\times \mathbf{64}$ CMOS Flash LiDAR Sensor with Push-Pull Analog Counter Achieving 0.1% Depth Uncertainty at 70m Detection Range
DOI
Dongseok Cho, Byungchoul Park, Hyun-Seung Choi, Myung-Jae Lee, Youngcheol Chae

Yonsei University · Korea Institute of Science and Technology
VLSI
2024

A 7.2inch 5.5Mpixel 600mW SPAD X-Ray Detector with 116.7 dB Dynamic Range
DOI
Byungchoul Park, Hyun-Seung Choi, Jinwoong Jeong, Jimin Cheon, Myung-Jae Lee, Youngcheol Chae

Yonsei University · Korea Institute of Science and Technology · Kumoh National Institute of Technology
VLSI
2024

A Wireless Neurostimulator Using Body-Coupled Link for Multisite Stimulation in Freely Behaving Animals
DOI
Taejune Jeon, Byeongseol Kim, Changuk Lee, Danbi Ahn, Daerl Park, Jaesuk Sung, Hee Young Kim, Heon-Jin Choi, Joonsung Bae, Youngcheol Chae

Yonsei University · Kangwon National University · University of California, Berkeley · Daegu Haany University
VLSI
2023

A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces
DOI
MoonHyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E.J. Chichilnisky, Boris Murmann, Dante G. Muratore

Stanford University · University of Macau · Yonsei University · Delft University of Technology
VLSI
2023

A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing
DOI
Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang

National Taiwan University · Yonsei University · The University of Texas at Austin · Tsinghua University
VLSI
2023

A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution
DOI
Hyeonho Han, Woojun Choi, Jaehyun Kim, Jaesuk Sung, Heon-Jin Choi, Youngcheol Chae

Yonsei University · ETH Zurich
VLSI
2023

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC
DOI
Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung Mo Moon, Kyomin Sohn, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2023

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications
DOI
Sekeon Kim, Keonhee Cho, Kyeongrim Baek, Hyunjun Kim, Younmee Bae, Mijung Kim, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2022

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications
DOI
Keonhee Cho, Giseok Kim, Jisang Oh, Kiryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung

Yonsei University · Samsung
VLSI
2022

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier
DOI
Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae

Yonsei University · Samsung
VLSI
2022

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM
DOI
Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Kiryong Kim, Byoung Mo Moon, Kyomin Sohn, Seong-Ook Jung

Yonsei University · Samsung