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企業・研究機関Company / Institute · · 2022–2026 LIVE

State Key Laboratory of ASIC and System

世界World 28位 (0 pt) · 対象論文Papers 17

年別の推移Papers per year

会議・論文誌別の論文数（フルカウント）Papers per venue (full count)

024682022 JSSC: 12022 ESSERC: 4520222023 JSSC: 42023 CICC: 12023 ESSERC: 2720232024 JSSC: 1120242025 JSSC: 4420252026
JSSCCICCESSERC
数値表を表示Show table
会議・論文誌Venue20222023202420252026
JSSC1414–
CICC–1–––
ESSERC42–––

会議・論文誌別By venue

順位はフルカウントでの値です。Ranks use the full count.

会議・論文誌VenueフルFull 筆頭First按分Frac. 順位Rank
ISSCC Tier 1000.00–
VLSI Tier 1000.00–
JSSC Tier 11093.72世界World #16
CICC Tier 2110.36世界World #22
A-SSCC Tier 2000.00–
ESSERC Tier 2662.45世界World #13

対象論文Papers

太字はこの機関の所属として確認できた著者です。Bold: authors affiliated with this institution.

  1. JSSC
    2025
    A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity
    DOI
    Heyu Ren, Liangjian Lyu, Binbin Chen, Wenjun Gong, Xing Wu, C.-J. Richard Shi
    Fudan University · State Key Laboratory of ASIC and System · East China Normal University · University of Washington
  2. JSSC
    2025
    A Hybrid Buck-or-Boost Converter for Fast-Transient and Wide-Voltage-Range Applications With Continuous Output Delivery Current
    DOI
    Junyi Ruan, Junmin Jiang, Chenzhou Ding, Kai Yuan, Ka Nang Leung, Zhiyuan Chen, Xiaoyang Zeng, Xun Liu
    Chinese University of Hong Kong, Shenzhen · Southern University of Science and Technology · Chinese University of Hong Kong · Fudan University · State Key Laboratory of ASIC and System
  3. JSSC
    2025
    A Sub-Nanosecond Pulsed VCSEL Driver With PVT-Compensated Constant Current, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety
    DOI
    Ming Zhong, Yifan Wu, Yuan Li, Wei Chen, Miao Sun, Liujia Song, Shanyu Cui, Xuefeng Chen, Patrick Yin Chiang, Shenglong Zhuo, Tao Xia
    Fudan University · State Key Laboratory of ASIC and System · Tongji University · Nanyang Technological University · Centre for Integrated Circuits and Systems · Peking University
  4. JSSC
    2025
    Enhancing Efficiency in Piezoelectric Energy Harvesting: Collaborative-Flip Synchronized Switch Harvesting on Capacitors Rectifier and Multioutput DC-DC Converters Utilizing Shared Capacitors
    DOI
    Jing Wang, Yi Yang, Zhen Li, Sijun Du, Xinling Yue, Xun Liu, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
    Fudan University · State Key Laboratory of ASIC and System · Delft University of Technology · Chinese University of Hong Kong, Shenzhen
  5. JSSC
    2024
    A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR
    DOI
    Cong Tao, Liangbo Lei, Chaoyang Zheng, Yumei Huang, Zhiliang Hong, Xiaoyang Zeng
    Fudan University · State Key Laboratory of ASIC and System
  6. CICC
    2023
    A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter
    DOI
    Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han
    Fudan University · State Key Laboratory of ASIC and System · University of Macau · Delft University of Technology
  7. ESSERC
    2023
    A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF
    DOI
    Renze Gan, Liangjian Lyu, C.-J. Richard Shi
    Fudan University · State Key Laboratory of ASIC and System · East China Normal University · University of Washington
  8. ESSERC
    2023
    A Sub-ns Pulsed VCSEL Driver with Real-Time Adaptive Current Control, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety
    DOI
    Tao Xia, Yuan Li, Liujia Song, Wei Chen, Hengwei Yu, Miao Sun, Lei Zhao, Zhihong Lin, Yuntong Tian, Hao Yan, Jiabin Meng, Yifan Wu, Yajie Qin, Xuefeng Chen, Shenglong Zhuo, Patrick Yin Chiang
    Fudan University · State Key Laboratory of ASIC and System · Tongji University
  9. JSSC
    2023
    A 0.5-mΩ/√Hz Dry-Electrode Bioimpedance Interface With Current Mismatch Cancellation and Input Impedance of 100 MΩ at 50 kHz
    DOI
    Qinjing Pan, Tianxiang Qu, Biao Tang, Fei Shan, Zhiliang Hong, Jiawei Xu
    Fudan University · State Key Laboratory of ASIC and System
  10. JSSC
    2023
    A 1.8–GΩ Input-Impedance 0.15–μV Input-Referred–Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction
    DOI
    Tianxiang Qu, Qinjing Pan, Liheng Liu, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu
    Fudan University · State Key Laboratory of ASIC and System
  11. JSSC
    2023
    A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS
    DOI
    Chunxiao Hu, Yun Yin, Tong Li, Yangzi Liu, Liang Xiong, Hongtao Xu
    Fudan University · State Key Laboratory of ASIC and System
  12. JSSC
    2023
    Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling
    DOI
    Shenglong Zhuo, Tao Xia, Lei Zhao, Miao Sun, Yifan Wu, Lei Wang, Hengwei Yu, Jiqing Xu, Jier Wang, Zhihong Lin, Yuan Li, Lei Qiu, Rui Bai, Xuefeng Chen, Patrick Yin Chiang
    Fudan University · State Key Laboratory of ASIC and System · Tongji University
  13. ESSERC
    2022
    A $130\mu \mathrm{W}$ Three-Step DT Incremental $\displaystyle \Delta\sum$ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range Counting
    DOI
    Lairong Fang, Yijie Li, Yao Zhang, Shuwen Zhang, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu
    Fudan University · State Key Laboratory of ASIC and System
  14. ESSERC
    2022
    A $136\mathrm{G}\Omega$-Input-Impedance Active Electrode for Non-Contact ECG Using Auto-Calibrated Positive Feedback and Capacitance Scaling in Femtofarad Resolution
    DOI
    Peizhuo Wang, Tianxiang Qu, Liangbo Lei, Zhiliang Hong, Jiawei Xu
    Fudan University · State Key Laboratory of ASIC and System
  15. ESSERC
    2022
    A 5.4-mW 50-MHz 29.3-dBm-IIP3 Fourth-Order Low-Pass Filter
    DOI
    Liangbo Lei, Cong Tao, Zhipeng Chen, Zhiliang Hong, Yumei Huang
    Fudan University · State Key Laboratory of ASIC and System
  16. ESSERC
    2022
    A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages
    DOI
    Peng Cao, Danzhu Lu, Jiawei Xu, Xiaoyang Zeng, Zhiliang Hong
    Fudan University · State Key Laboratory of ASIC and System
  17. JSSC
    2022
    A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement
    DOI
    Yicheng Li, Yun Yin, Diyang Zheng, Xianglong Jia, Jie Lin, Fu Gao, Yiting Zhu, Liang Xiong, Na Yan, Ye Lu, Hongtao Xu
    Fudan University · State Key Laboratory of ASIC and System